38 single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi micr ocomputers 4 5 set value of the start bit position register 5 reference clock period < fig. 31. caption position register (6) reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit i s input to the reference voltage generating circuit and the comparat or. reference voltage generating circuit this circuit generates a reference voltage (slice voltage) b y using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. connect a capacitor betwee n the v hold pin and the v ss pin, and make the length of wiring as short as possible so that a leakage current may not be generated. comparator the comparator compares the voltage of the composite video s ignal with the voltage (reference voltage) generated in the refere nce voltage generating circuit, and converts the composite video signal into a digital value. (7) start bit detecting circuit this circuit detects a start bit at line decided in the data slice line specification circuit. for start bit detection, it is possib le to select one of the following two types by using bit 1 of clock run-in r egister 2 (address 00e7 16 ). after the lapse of the time corresponding to the set value o f the start bit position register (address 00e1 16 ), the first rising of the composite video signal is detected as a start bit. the time is set in bits 0 to 6 of the start bit position reg ister (address 00e1 16 ) (refer to figure 32). set a value fit for the following conditions. figure 32 shows the structure of the start bit position regi ster. time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in fig. 32. start bit position register caption position register (cp : address 00e0 16 ) specification main data slice line 70 100 fix these bits to 100 2 70 start bit generating time time from a falling of the horizontal synchronizing signal to occurrence of a start bit = 4 5 set value (00 16 to 7f 16 ) 5 reference clock period start bit position register (sp : address 00e1 16 ) dsc1 bit 7 control bit 0 : generation of 16 pulses 1 : generation of 16 pulses and detection of clock run-in pulse (4 to 6 pulses) time from the faling of the horizontal synchronous signal to occurrence of the start bit <
39 single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi micr ocomputers after a falling of the clock run-in pulse set in bits 2 to 0 of clock run- in detect register 2 (address 00e9 16 ) is detected, a start bit is detected by sampling a comparator output. a sampling clock f or sampling is obtained by dividing the reference clock generat ed in the timing signal generating circuit by 13. figure 34 shows the structure of clock run-in detect registe r 2. the contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronous signal. for this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritte n until a falling of the horizontal synchronous signal. fig. 33. clock run-in register 2 (8) clock run-in determination circuit this circuit sets a window in the clock run-in portion in th e composite video signal, and then determinates clock run-in by counting the number of pulses in this window. set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00e2 16 ; refer to figure 35). the window ends according to the contents of the setting of the start bit position register (refer to figure 32). fig. 35. window register fig. 34. clock run-in detect register 2 70 1 start bit detecting method selection bit 0 : method 1 1 : method 2 clock run-in register 2 (cr2 : address 00e7 16 ) fix this bit to 1 fix these bits to 100111 2 0 0111 1 70 clock run-in pulses for sampling b2 b1 b0 0 0 0 : not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse clock run-in detect register 2 (crd2 : address 00e9 16 ) data clock generating time time from detection of a start bit to occurrence of a data clock = (13 + set value) 5 reference clock period 70 window start time time from a falling of the horizontal synchronizing signal to a start of the window = 4 5 set value (00 16 to 3f 16 ) 5 reference clock period window register (wn : address 00e2 16 ) fix these bits to 0 00
40 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 36. clock run-in register 1 fig. 39. clock run-in detect registers 1 and 3 fig. 38. window setting fig. 37. clock run-in register 3 for the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00e6 16 ; refer to figure 36). for the sub-data slice line, the count value of pulses in the window is stored in clock run-in register 3 (address 0209 16 ; refer to figure 37). when this count value is 4 to 6, it is determined as a clock run-in. accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to figure 38). the contents to be set in the window register are written at a falling of the horizontal synchronous signal. for this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronous signal. for the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of clock run-in detect register 2 (address 00e9 16 ) to the next falling. the count value is stored in bits 3 to 7 of clock run-in detect register 1 (address 00e8 16 ) (when the count value exceeds 1f 16 , 1f 16 is held). for the sub-data slice line, the count value is stored in bits 3 to 7 of clock run-in detect register 3 (address 0208 16 ). read out these bits after the occurence of a data slicer interrupt (refer to (11) interrupt request generating circuit). figure 39 shows the structure of clock run-in detect registers 1 and 3. 70 clock run-in count value of main-data slice line clock run-in register 1 (cr1 : address 00e6 16 ) fix these bits to 0101 2 0101 7 clock run-in count value of sub-data slice line clock run-in register 3 (cr3 : address 0209 16 ) data latch completion flag for caption data in i sub-data slice line 0: data is not latched yet 1: data is latched data slice line selection bit for interrupt request 0: main data slice line 1: sub-data slice line interrupt mode selection bit 0: interrupt occurs at end of data slice line a 1: interrupt occurs at completion of caption data latch ] when the count value in the window is 4 to 6, this is determined as a clock run-in. horizontal synchronous signal composite video signal window clock run-in start bit data + 16-bit data time to be set in the window register time to be set in the start bit position register 70 number of reference clocks to be counted in one clock run-in pulse period clock run-in detect registers 1, 3 ( crd1 : address 00e8 16 ) ( crd3 : address 0208 16 ) test bits : read-only 0
41 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers conditions for setting bit 4 of dsc3 to 1 data clock of 16 pulses has occured in sub-data slaice line data clock of 16 pulses has occured in sub-data slaice line and clock run-in pulse are detected 4 to 6 times (10) 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. for the main data slice line, the contents of the high-order 8 bits of the stored caption data and the contents of the low-order 8 bits of the same data can be obtained by reading out data register 2 (address 00e5 16 ) and data register 1 (address 00e4 16 ), respectively. for the sub-data slice line, the contents of the high-order 8 bits and the contents of the low-order 8 bits can be obtained by reading out the data register 4 (address 00ed 16 ) and data register 3 (address 00ec 16 ), respectively. these registers are reset to 0 at a falling of v sep . read out data registers 1 and 2 after the occurence of a data slicer interrupt (refer to (11) interrupt request generating circuit). (11) interrupt request generating circuit the interrupt requests as shown in table 6 are generated by combination of the following bits; bits 5 and 6 of the clock run-in register 3 (address 0209 16 ), bit 1 of the clock run-in register 2 (address 00e7 16 ). read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of clock run-in detect registers 1 and 3 after the occurence of a data slicer interrupt request. for a data clock, 16 pulses are generated. when just 16 pulses have been generated, bit 7 of the data slicer control register is set to 1 (refer to figure 26). when method 1 is already selected as a start bit detecting method, this bit becomes a logical product (and) value with a clock run-in determination result by setting bit 7 of the start bit position register to 1. when method 2 is already selected as a start bit detecting method and 16 pulses are generated of a data clock regardless of bit 7 of the start bit position register, this bit is set to 1. the contents of this bit are reset at a falling of the vertical synchronizing signal (v sep ). table 5. setting conditions for caption data latch completion flag bit 7 of sp 0 1 conditions for setting bit 7 of dsc1 to 1 data clock of 16 pulses has occured in main data slaice line data clock of 16 pulses has occured in main data slaice line and clock run-in pulse are detected 4 to 6 times (9) data clock generating circuit this circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. set the time from detection of the start bit to occurrence of the data clock in bits 3 to 7 of clock run-in detect register 2 (address 00e9 16 ). the time to be set is represented by the following expression: time = (13 + set value) 5 reference clock period slice line main data slice line sub-data slice line b5 0 1 sources at end of data slice line data clock of 16 pulses has occured and clock run-in pulse are detected 4 to 6 times data clock of 16 pulses has occured at end of data slice line data clock of 16 pulses has occured and clock run-in pulse are detected 4 to 6 times data clock of 16 pulses has occured b6 0 1 0 1 cr2 b1 0 1 0 1 0 1 0 1 cr3 table 6. occurence sources of interrupt request occurence souces of interrupt request
42 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 40. sync pulse counter register (12) synchronous signal counter the synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal v sep as a count source. the count value in a certain time (t time) generated by f(x in )/2 13 or f(x in )/2 13 is stored into the 5-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds 1f 16 , 1f 16 is stored into the latch. the latch value can be obtained by reading out the sync pulse counter register (address 020f 16 ). a count source is selected by bit 5 of the sync pulse counter register. the synchronous signal counter is used when bit 0 of pwm mode register 1 (address 02ea 16 ). figure 40 shows the structure of the sync pulse counter and figure 41 shows the synchronous signal counter block diagram. fig. 41. synchronous signal counter block diagram sync pulse counter register (syc : address 020f 16 ) count value count source count time 0: h sync signal 1: composite sync signal f(x in )/2 13 (1024 s, f(x in ) = 8 mhz) 70 reset 5-bit counter latch (5 bits) f(x in )/2 13 composite sync signal h sync signal counter sync pulse counter register data bus selection gate : connected to black colored side when reset. b5
43 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 7. multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note: we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the con- trol function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 42 shows a block diagram of the multi-master i 2 c-bus inter- face and table 7 shows multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 42. block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c clock control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2
44 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw slave address i 2 c address register (s0d: address 00f7 16 ) read/write bit 70 (1) i 2 c data shift register the i 2 c data shift register (s0 : address 00f6 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00f9 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f8 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. (2) i 2 c address register the i 2 c address register (address 00f7 16 ) consists of a 7-bit slave ___ address and a read /write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. ____ n bit 0: read /write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. (3) i 2 c clock control register the i 2 c clock control register (address 00fa 16 ) is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 7. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit gener- ated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. fig. 43. i 2 c address register
45 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. table 8. set values of i 2 c clock control register and scl frequency (4) i 2 c control register the i 2 c control register (address 00f9 16 ) controls the data commu- nication format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. n bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00f8 16 ). ? writing data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to (5) i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. n bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 46). fig. 44. i 2 c clock control register scl frequency (at = 4mhz, unit : khz) setting value of ccr4Cccr0 standard clock mode setup disabled setup disabled setup disabled setup disabled setup disabled 100 83.3 500/ccr value 17.2 16.6 16.1 high-speed clock mode setup disabled setup disabled setup disabled 333 250 400(note) 166 1000/ccr value 34.5 33.3 32.3 ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 note: at 400 khz in the high-speed clock mode, the duty is as be- low. low period : high period = 3 : 2 in the other cases, the duty is 50%. ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 00fa 16 ) 7 scl frequency control bits refer to table 8. scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock 0
46 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. fig. 46. i 2 c control register (5) i 2 c status register the i 2 c status register (address 00f8 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by execut- ing a write instruction to the i 2 c data shift register (address 00f6 16 ). n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start con- dition. ] general call: the master transmits the general call address 00 16 to all slaves. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start condition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00f7 16 ). ? a general call is received. in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address register (8 bits consists of slave address and rbw), the first bytes match. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). fig. 45. connection port control by bsel0 and bsel1 0 1 bsel0 scl1/p1 1 scl2/p1 2 0 1 bsel1 0 1 bsel0 sda1/p1 3 sda2/p1 4 0 1 bsel1 multi-master i 2 c-bus interface scl sda 7 bsel1 bsel0 10 bit sad als eso bc2 bc1 bc0 0 connection control bits between i 2 c-bus interface and ports b7 b6 connection port 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1, scl2, sda2 i 2 c control register (s1d : address 00f9 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 i 2 c-bus interface use enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format note: when using multi-master i 2 c-bus interface, set bits 3 and 4 of the serial i/o mode register (address 0213 16 ) to 1. moreover, set the corresponding direction register to 1 to use the port as multi-master i 2 c-bus interface.
47 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. n bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when a device other than the mi- crocomputer sets the sda to l,, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. ] arbitration lost: the status in which communication as a master is disabled. n bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 40 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00f6 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condi- tion duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00f9 16 ) is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 __ (transmit) if the least significant bit (r/w bit) of the address data trans- __ mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset n bit 7: communication mode specification bit (master/slave speci- fication bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when ar- bitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: ? a start condition is set by another master device.
48 mitsubishi microcomputers single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. (6) start condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) to set the mst, trx and bb bits to 1. a start condition w ill then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 49 for the start condition gen- eration timing diagram, and table 9 for the start condition/ stop condition generation timing table. fig. 49. start condition generation timing diagram fig. 48. interrupt request signal generation timing fig. 47. i 2 c status register (7) restart condition generation method to generate the restart condition, take the following sequen ce: set 20 16 to the i 2 c status register (s1). write a transmit data to the i 2 c data shift register. set f0 16 to the i 2 c status register (s1) again.
49 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. (9) start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 51 and table 10. only when the 3 conditions of table 10 are satis- fied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. (8) stop condition generation method when the es0 bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 50 for the stop condition generation timing diagram, and table 9 for the start condition/stop condition generation timing table. fig. 50. stop condition generation timing diagram fig. 51. start condition/stop condition detect timing diagram standard clock mode 6.5 s (26 cycles) < scl release time 3.25 s (13 cycles) < setup time 3.25 s (13 cycles) < hold time high-speed clock mode 1.0 s (4 cycles) < scl release time 0.5 s (2 cycles) < setup time 0.5 s (2 cycles) < hold time table 10. start condition/stop condition detect conditions table 9. start condition/stop condition generation timing table item setup time hold time set/reset time for bb flag standard clock mode 5.0 s (20 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) high-speed clock mode 2.5 s (10 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. i 2 c status register write signal reset time for bb flag hold time setup time scl sda bb flag hold time setup time scl sda (start condition) sda (stop condition) scl release time hold time setup time
50 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. (10) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00f7 16 ) is not made. for the data transmission format when the 7-bit address- ing format is selected, refer to figure 52, (1) and (2). 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 1. an address compari- son is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, an ad- dress comparison between the rbw bit of the i 2 c address regis- __ ter (address 00f7 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit __ addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00f8 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00f6 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00f7 16 ) to 1 by software. this __ processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00f7 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 52, (3) and (4). (11) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00fa 16 ). a set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. ? set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00f6 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (address 00f8 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. ? set transmit data in the i 2 c data shift register (address 00f6 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 c status register (address 00f8 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. (12) example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00fa 16 ). a set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. ? set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). ? when a start condition is received, an address comparison is made. ? ?when all transmitted addresses are 0 (general call) : ad0 of the i 2 c status register (address 00f8 16 ) is set to 1 and an interrupt request signal occurs. ?when the transmitted addresses match the address set in : aas of the i 2 c status register (address 00f8 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above : ad0 and aas of the i 2 c status register (address 00f8 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 00f6 16 ). ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends.
51 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. fig. 52. address data communication format s slave address a data a data a/a p r/w 7 bits ? 1 to 8 bits 1 to 8 bits s slave address a data a data ap 7 bits ? 1 to 8 bits 1 to 8 bits (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits ? 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter slave address 2nd byte a data a/a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits ? 8 bits 7 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data ap 1 to 8 bits ? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition p : stop condition a : ack bit r/w : read/write bit sr : restart condition from master to slave from slave to master r/w r/w r/w r/w
52 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers osd mode (on-screen display mode) 36 characters 5 12 lines 16 5 20 dots 14 kinds 5 1, 5 2, 5 3 1t c 5 1/2h, 1t c 5 1h, 1.5t c 5 1/2h, 1.5t c 5 1h, 2t c 5 2h, 3t c 5 3h border 1 screen : 7 kinds, max. 7 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, out1, out2 dual layer osd function (layer 2) possible osd functions table 11 outlines the osd functions of the m37271mf-xxxsp. the m37274ma-xxxsp incorporates an osd circuit of 36 charac- ters 5 12 lines. osd is controlled by the osd control register. there are 3 display modes and they are selected by a block unit. the dis- play modes are selected by block control register i (i = 1 to 12). the features of each mode are described below. exosd mode (extra on-screen display mode) 36 characters 5 12 lines 16 5 26 dots 6 kinds 5 1, 5 2, 5 3 1t c 5 1/2h, 1t c 5 1h border, extra font (16 kinds) 1 screen : 5 kinds, max. 5 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, out1, out2 possible cc mode (closed caption mode) 36 characters 5 12 lines 16 5 26 dots (character dot structure : 20 5 16 dots) 2 kinds 5 1, 5 2 1t c 5 1/2h smooth italic, under line, flash 1 screen : 7 kinds, max. 7 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, out1, out2 auto solid space function window function dual layer osd function (layer 1) possible parameter number of display characters character display area kinds of characters kinds of character sizes attribute character font coloring raster coloring character background coloring border coloring extra font coloring osd output function display expansion (multiline display) pre-divide ratio (note) dot size table 11. features of each display mode display mode 256 kinds (in exosd mode, they can be combined with 16 kinds of extra fonts) notes 1: the divide ratio of the frequency divider (the pre-divide circuit) is referred as pre-divide ratio hereafter. 2: the character size is specified with dot size and pre-divide ratio (refer to (3) dote size). note : note that eprom version has 40 characters 5 16 lines when programming.
53 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers the osd circuit has an extended display mode. this mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 53 shows the configuration of osd character. figure 54 shows the block diagram of the osd circuit. figure 55 shows the structure of the osd control register. figure 56 shows the structure of the block control register. fig. 53. configuration of osd character display area 16 dots 26 dots 20 dots underline area * blank area * * : displayed only in ccd mode. blank area * 26 dots 20 dots character font 26 dots 20 dots osd mode cc mode extra font exosd mode 16 dots 16 dots 16 dots 16 dots logical sum (or)
54 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 54. block diagram of osd circuit h sync v sync ram for osd 20 bytes 5 36 characters 5 12 lines data bus rom for osd ( 16 dots 5 20 dots 5 256 characters) + 16 dots 5 26 dots 5 16 characters) shift register 2 16-bit shift register 1 16-bit clock for osd output circuit r g b osd control circuit out1 out2 control registers for osd (address 00ce 16 ) (address 00cf 16 ) (addresses 00d0 16 to 00db 16 ) (address 0216 16 ) (address 0217 16 ) (address 0218 16 ) (address 0219 16 ) (address 021b 16 ) (addresses 021c 16 to 021f 16 ) (addresses 0220 16 to 023b 16 ) osd control register horizontal position register block control registers clock source control register i/o polarity control register raster color register extra font color register border color register window h/l registers vertical position registers display oscillation circuit osc1 osc2 data slicer clock oscillation circuit x in x out main clock
55 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers display layer layer 1 layer 2 dot size 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 1t c 5 1/2h 1t c 5 1h 1.5t c 5 1/2h 1.5t c 5 1h b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 b4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b6 0 0 1 1 1 table 12. setting value of block control registers pre-divide ratio 5 1 5 2 5 3 5 1 5 2 b5 0 1 0 1 1 cs 6 0 1 notes 1: cs 6 : bit 6 of clock control register (address 0216 16 ) 2: t c : osd clock cycle divided in the pre-divide circuit 3: h: h sync fig. 56. block control registers fig. 55. osd control register flash mode selection bit 0 : color signal of character background part does not flash 1 : color signal of character background part flashes 7 osd control register (oc : address 00ce 16 ) osd control bit (note 1) 0 : all-blocks display off 1 : all-blocks display on scan mode selection bit 0 : normal scan mode 1 : bi-scan mode border type selection bit 0 : all bordered 1 : shadow bordered (note 2) automatic solid space control bit 0 : off 1 : on window control bit 0 : off 1 : on layer mixing control bits (note 3) b7 b6 0 0 : logical sum (or) of layer 1s color and layer 2s color 0 1 : layer 1s color has priority 1 0 : layer 2s color has priority 1 1 : do not set notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2 : shadow border is output at right and bottom side of the font. 3 : set 00 during displaying extra fonts. 7 block control register i (i = 1 to 12) (bci : addresses 00d0 16 to 00bf) display mode selection bits b1 b0 0 0 : display off 0 1 : osd mode 1 0 : cc mode 1 1 : exosd mode border control bit 0 : border off 1 : border on notes 1: bit rc 14 of osd ram controls out1 output when bit 7 is 0. bit rc 14 of osd ram controls out2 output when bit 7 is 1. 2: note that eprom version the block control registers at addresses 00d0 16 to 00df 16 when programming. dot size selection bit refer to table 12. pre-divide ratio ? layer selection bits refer to table 12. out 2 output control bit (note) 0 : out2 output off 1 : out2 output on 0 0
56 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers osd mode same as layer 1 same as layer 1 (note) pre-divide ratio = 1 pre-divide ratio = 2 1t c 5 1/2h 1t c 5 1/2h, 1.5t c 5 1/2h 1t c 5 1h 1t c 5 1h, 1.5t c 5 1h same position as layer 1 (1) dual layer osd m37274ma-xxxsp has 2 layers; layer 1 and layer 2. these layers display the osd for controlling tv and the closed caption display at the same time and overlayed on each other. each block can be assigned to either layer by bits 6 and 5 of the block control register (refer to figure 56). for example, only when both bits 5 and 6 are 1, the block is assigned to layer 2. other bit combinations assign the block to layer 1. when a block of layer 1 is overlapped with that of layer 2, a screen is combined (refer to figure 58) by bits 7 and 6 of the osd control register (refer to figure 55). note: when using the dual layer osd, note table 13. fig. 57. image of dual layer osd cc mode data slicer clock or osc1 or main clock 5 1 or 5 2 (all blocks) 1t c 5 1/2h arbitrary display mode osd clock source pre-divide ratio dot size horizontal display start position table 13. conditions of dual layer note: for the pre-divide ratio of the layer 2, select the same as the layer 1s ratio by bit 6 of the clock control register. block in layer 1 block in layer 2 fig. 58. display example of dual layer osd block parameter display example of layer 1 = hello, layer 2 = ch5 ch5 hello logical sum (or) of layer 1s color and layer 2s color bit 7 = 0, bit 6 = 0 layer 1s color has priority bit 7 = 0, bit 6 = 1 ch5 hello layer 2s color has priority bit 7 = 1, bit 6 = 0 hello ch5 layer 2 layer 1 block 1 block 2 block 7 block 8 ... block 9 block 10 block 11 block 12 block block
57 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (2) display position the display positions of characters are specified by a block. there are 12 blocks, blocks 1 to 12. up to 36 characters can be displayed in each block (refer to (6) memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 t osc (t osc = osd oscillation cycle). the display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 t h ( t h = h sync cycle). blocks are displayed in conformance with the following rules: when the display position is overlapped with another block (figure 59, (b)), a lower block number (1 to 12) is displayed on the front. when another block display position appears while one block is displayed (figure 59 (c)), the block with a larger set value as the vertical display start position is displayed. however, do not dis- play block with the dot size of 2t c 5 2h or 3t c 5 3h during dis- play period ( ] ) of another block. ] in the case of osd mode block: 20 dots in vertical from the verti- cal display start position. ] in the case of cc or exosd mode block: 26 dots in vertical from the vertical display start position. fig. 59. display position (hr) vp12, vp22 block 1 block 2 (a) example when each block is separated vp13, vp23 block 3 (hr) vp11, vp12 = vp21, vp22 block 1 (b) example when block 2 overlaps with block 1 (block 2 is not displayed) (hr) vp11, vp21 vp12, vp22 (c) example when block 2 overlaps in process of block 1 block 1 block 2 note: vp1i or vp2i (i : 1 to 12) indicates the vertical display start position of display block i. vp11, vp21
58 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers the display position in the vertical direction is determined by count- ing the horizontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the i/o polarity control register (address 0217 16 ). fig. 60. supplement explanation for display position the vertical position for each block can be set in 1024 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to ff 16 in vertical position register 1i (i = 1 to 12) (addresses 0220 16 to 022b 16 ) and values 00 16 to 03 16 in vertical position register 2i (i = 1 to 12) (addresses 0230 16 to 023b 16 ). the structure of the vertical position registers is shown in figure 61. fig. 61. vertical position registers the horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4t osc , t osc being the oscillating cycle for display) as values 00 16 to ff 16 in bits 0 to 7 of the horizontal position register (address 00cf 16 ). the structure of the horizontal position register is shown in figure 62. fig. 62. horizontal position register when bits 0 and 1 of the i/o polarity control register (address 0217 16 ) are set to 1 (negative polarity) v sync signal input v sync control signal in microcomputer 0.25 to 0.50 [ m s] ( at f(x in ) = 8mhz) period of counting h sync signal (note 2) h sync signal input not count 12345 notes 1 : the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer. 2 : do not generate falling edge of h sync signal near rising edge of v sync control signal in microcomputer to avoid jitter. 3 : the pulse width of v sync and h sync needs 8 machine cycles or more. 8 machine cycles or more 8 machine cycles or more 7 vertical position register 1i (i = 1 to 12) (vp1i : addresses 0220 16 to 022b 16 ) control bits of vertical display start positions (note) vertical display start positions (low-order 8 bits) t h 5 (setting value of low-order 2 bits of vp2i 5 16 + setting value of low-order 4 bits of vp1i 5 16 + setting value of low-order 4 bits of vp1i 5 16 ) note : set values except 00 16 and 01 16 to vp1i when vp2i is 00 16. 2 1 0 7 vertical position register 2i (i = 1 to 12) (vp2i : addresses 0230 16 to 023b 16 ) control bits of vertical display start positions (note) vertical display start positions (high-order 2 bits) t h (setting value of low-order 2 bits of vp2i 5 16 setting value of low-order 4 bits of vp1i 5 16 setting value of low-order 4 bits of vp1i 5 16 ) 2 1 0 note : the setting value synchronizes with the v sync . 7 horizontal position register (hp : address 00cf 16 ) control bits of horizontal display start positions horizontal display start positions 4t osc 5 (setting value of high-order 4 bits 5 16 + setting value of low-order 4 bits 5 16 ) 1 0 5 + + 0 0 0
59 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers notes 1 : 1t c (t c : osd clock cycle divided by prescaler) gap oc- curs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accordingly, when 2 blocks have different pre- divide ratios, their horizontal display start position will not match. ordinaly, this gap is 1t c regardless of character sizes, however, the gap is 1.5t c only when the character size is 1.5t c . 2 : the horizontal start position is based on the osd clock source cycle selected for each block. accordingly, when 2 blocks have different osd clock source cycles, their hori- zontal display start position will not match. fig. 63. notes on horizontal display start position h sync 1t c 1t c block 1 (pre-divide ratio 1, clock source data slicer clock) 1t c 1t c 4t osc 5 n 4t osc 5 n note 1 note 2 block 2 (pre-divide ratio 2, clock source data slicer clock) block 3 (pre-divide ratio 3, clock source = data slicer clock) block 5 (pre-divide ratio 3, clock source osc1) block 4 (pre-divide ratio 2, character size 1.5tc, clock source data slicer clock) 1.5t c : value of horizontal position register (decimal notation) : osd clock cycle divided in the pre-divide circuit : osd oscillation cycle : 62 tosc n 1tc tosc tdef = = = = = = = = = =
60 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (3) dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size con- trol circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, osc1, main clock) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size of the layer 1 is specified by bits 6 to 3 of the block control register. the dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. refer to figure 56 (the structure of the block control regis- ter), refer to figure 65 (the structure of the clock source control reg- ister). the block diagram of dot size control circuit is shown in figure 64. notes 1 : the pre-divide ratio = 3 cannot be used in the cc mode. 2 : the pre-divide ratio of the osd mode block on the layer 2 must be same as that of the cc mode block on the layer 1 by bit 6 of the clock source control register. 3 : in the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. refer to (13) scan mode about the scan mode. fig. 64. block diagram of dot size control circuit fig. 65. definition of dot sizes h sync main clock synchronous cycle 5 2 circuit cycle 5 3 pre-divide circuit clock cycle = 1t c horizontal dot size control circuit vertical dot size control circuit osd control circuit data slicer clock (note) osc1 note: to use data slicer clock, set bit 0 of data slicer control register to ?. 1 dot scanning line of f1(f2) scanning line of f2(f1) 1/2h 1h 2h 3h 3t c 2t c 1t c 1t c
61 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers input port 1 0 1 (4) clock for osd as a clock for display to be used for osd, it is possible to select one of the following 4 types. ? main clock (8 mhz) ? data slicer clock output from the data slicer (approximately 26 mhz) ? clock from the lc oscillator supplied from the pins osc1 and osc2 ? clock from the ceramic resonator or the quartz-crystal oscillator from the pins osc1 and osc2 this osd clock for each block can be selected by the following bits : bit 7 of the port p3 direction register, bits 5 and 4 of the clock source control register (addresses 0216 16 ). a variety of character sizes can be obtained by combining dot sizes with osd clocks. when not us- ing the pins osc1 and osc2 for the osd clock i/o pins, the pins can be used as sub-clock i/o pins or port p6. fig. 67. block diagram of osd selection circuit fig. 66. clock control register table 14. setting for p6 3 /osc1/x cin , p6 4 /osc2/x cout b7 of port p3 direction register clock source control register osd clock i/o pin 0 11 01 b5 b4 sub-clock i/o pin 0 0 0 function register notes 1: when setting 10 2 , main clock is set as a clock in the cc mode and exosd mode regardless of bits 0, 3. 2: be sure to set bit 7 to 0 for program of the mask and the eprom versions. for the emulator mcu version (m37274erss), be sure to set bit 7 to 1 when using the data slicer clock for software debugging. 7 clock source control register (cs : address 0216 16 ) cc mode clock selection bit 0 : data slicer clock 1 : osc1 clock osd mode clock selection bits b2 b1 0 0 : data slicer clock 0 1 : osc1 clock 1 0 : main clock (note 1) 1 1 : do not set exosd mode clock selection bit 0 : data slicer clock 1 : osc1 clock pre-divide ratio of layer 2 selection bit 0 : 5 1 1 : 5 2 test bit (note 2) osd1 oscillating mode selection bits b5 b4 0 0 : 32 kh z oscillating mode 0 1 : input ports p6 3 , p6 4 1 0 : lc oscillating mode 1 1 : ceramic ? quartz-crystal oscillating mode 0 11 10 0 0 32 kh z data slicer circuit data slicer clock osc1 clock lc ceramic ? quartz-crystal oscillating mode for osd cs5 , cs4 00 1 1 1 cs0 cs1 cs3 cs2 = 0 cc mode block osd mode block exosd mode block except 10 10 10 cs2, cs1 except 10 clock oscillation circuit main clock except 10 cs2, cs1 cs2, cs1 (note) note : to use data slicer clock, set bit 0 of data slicer control register to 1. 0
62 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (5) field determination display to display the block with vertical dot size of 1/2h, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. the dot line 0 or 1 (re- fer to figure 69) corresponding to the field is displayed alternately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. a field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure 60) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the comparing time, it is regarded as even field. when the time is shorter, it is re- garded as odd field the contents of this field can be read out by the field determination flag (bit 7 of the i/o polarity control register at address 0217 16 ). a dot line is specified by bit 6 of the i/o polarity control register (refer to figure 69). however, the field determination flag read out from the cpu is fixed to 0 at even field or 1 at odd field, regardless of bit 6. fig. 68. i/o polarity control register 0 7 i/o polarity control register (pc : address 0217 16 ) h sync input polarity switch bit 0 : positive polarity input 1 : negative polarity input out2 output polarity switch bit 0 : positive polarity output 1 : negative polarity output v sync input polarity switch bit 0 : positive polarity input 1 : negative polarity input r/g/b output polarity switch bit 0 : positive polarity output 1 : negative polarity output out1 output polarity switch bit 0 : positive polarity output 1 : negative polarity output display dot line selection bit (note) field determination flag 0 : even field 1 : odd field note : refer to figure 69. at odd field at odd field 1 : at even field 0 : at even field
63 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 69. relation between field determination flag and display font both h sync signal and v sync signal are negative-polarity input field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, be sure to set bit 0 of the pwm mode register 1 (address 020a 16 ) to 0. t2 t3 osd rom font configuration diagram dot line 0 dot line 1 odd dot line 0 dot line 1 (n C 1) field (odd-numbered) t1 0.25 to 0.50[ m s] at f(x in ) = 8 mhz cc mode exosd mode 13579111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 2 4 6 8 10 12 14 16 osd mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n + 1) field (odd-numbered) when the display dot line selection bit is 0, the font is displayed at even field, the font is displayed at odd field. bit 7 of the i/o polarity control register can be read as the field determination flag : 1 is read at odd field, 0 is read at even field. note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer.
64 single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (6) memory for osd there are 2 types of memory for osd : rom for osd (addresses 10800 16 to 155ff 16 , 18000 16 to 1e41f 16 ) used to store character dot data (masked) and ram for osd (addresses 0800 16 to 0df3 16 ) used to specify the characters and colors to be displayed. t he fol- lowing describes each type of memory. rom for osd (addresses 10800 16 to 155ff 16 , 18000 16 to 1e43f 16 ) the rom for osd contains dot pattern data for characters to be displayed. to actually display the character code and the ex tra code stored in this rom, it is necessary to specify them by writi ng the character code inherent to each character (code determined b ased on the addresses in the rom for osd) into the ram for osd. the osd rom of the character font has a capacity of 11072 by tes. since 40 bytes are required for 1 character data, the rom ca n stores up to 256 kinds of characters. the osd rom of the extra font has a capacity of 832 bytes. since 52 bytes are required for 1 cha racter data, the rom can stores up to 16 kinds of characters. data of the character font and extra font is specified shown in figure 70. fig. 70. osd character data storing form osd rom address of character font data ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 line number character code font bit = 02 16 to 15 16 = 00 16 to 13f 16 = 0 : left font 1 : right font osd rom address bit line number/character code/font bit 10 line number character code font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 11 00 00 02 16 0000 16 7ff0 16 7ff8 16 601c 16 600c 16 600c 16 600c 16 600c 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 0a 16 601c 16 7ff8 16 7ff0 16 6300 16 6380 16 61c0 16 60e0 16 6070 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 6038 16 601c 16 600c 16 0000 16 15 16 12 16 13 16 14 16 b0 b7 b0 b7 02 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 0a 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 0003 16 0003 16 0003 16 0003 16 15 16 12 16 13 16 14 16 b0 b7 b0 b7 ffff 16 fffe 16 0000 16 0000 16 19 16 16 16 17 16 18 16 00 16 01 16 fffe 16 ffff 16 line number line number extra code font bit 00 16 to 19 16 00 16 to 1f 16 0 : left font 1 : right font osd rom address bit line number/extra code /font bit extra code line number left font right font line number data in osd rom left font right font data in osd rom osd rom address of extra font data character font extra font font bit 0 0 = = =
65 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers character code specification 0800 16 0801 16 : 0817 16 0818 16 : 0822 16 0823 16 0880 16 0881 16 : 0897 16 0e98 16 : 08a2 16 08a3 16 0900 16 0901 16 : 0917 16 0918 16 : 0922 16 0923 16 0980 16 0981 16 : 0997 16 0998 16 : 09a2 16 09a3 16 0a00 16 0a01 16 : 0a17 16 0a18 16 : 0a22 16 0a23 16 color code 2 specification 0828 16 0829 16 : 083f 16 0868 16 : 0872 16 0873 16 08a8 16 08a9 16 : 08bf 16 08e8 16 : 08f2 16 08f3 16 0928 16 0929 16 : 093f 16 0968 16 : 0972 16 0973 16 09a8 16 09a9 16 : 09bf 16 09e8 16 : 09f2 16 09f3 16 0a28 16 0a29 16 : 0a3f 16 0a68 16 : 0a72 16 0a73 16 display position (from left) 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character block block 1 block 2 block 3 block 4 block 5 table 15. contents of osd ram ram for osd (addresses 0800 16 to 0df3 16 ) the ram for osd is allocated at addresses 0800 16 to 0df3 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. table 15 shows the contents of the ram for osd. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0800 16 , write color code 1 at 0840 16 , and write color code 2 at 0828 16 . the structure of the ram for osd is shown in figure 72. note: for the osd mode block with dot size of 1.5t c 5 1/2h and 1.5t c 5 1h, the 3nth (n = 1 to 13) character is skipped as compared with ordinary block ] . accordingly, maximum 24 char- acters are only displayed in 1 block. the ram data for the 3nth character does not effect the display. any character data can be stored here (refer to figure 71). note that eprom version has maximum 27 characters (the right 1/3 part of the 27th's character area is not displayed.) in 1 block when programming. ] blocks with dot size of 1t c 5 1/2h and 1t c 5 1h, or blocks on the layer 1 color code 1 specification 0840 16 0841 16 : 0857 16 0858 16 : 0862 16 0863 16 08c0 16 08c1 16 : 08d7 16 08d8 16 : 08e2 16 08e3 16 0940 16 0941 16 : 0957 16 0958 16 : 0962 16 0963 16 09c0 16 09c1 16 : 09d7 16 08d8 16 : 09e2 16 09e3 16 0a40 16 0a41 16 : 0a57 16 0a58 16 : 0a62 16 0a63 16 2
66 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers table 15. contents of osd ram (continued) color code 2 specification 0aa8 16 0aa9 16 : 0abf 16 0ae8 16 : 0af2 16 0af3 16 0b28 16 0b29 16 : 0b3f 16 0b68 16 : 0b72 16 0b73 16 0ba8 16 0ba9 16 : 0bbf 16 0be8 16 : 0bf2 16 0bf3 16 0c28 16 0c29 16 : 0c3f 16 0c68 16 : 0c72 16 0c73 16 0ca8 16 0ca9 16 : 0cbf 16 0ce8 16 : 0cf2 16 0cf3 16 0d28 16 0d29 16 : 0d3f 16 0d68 16 : 0d72 16 0d73 16 0da8 16 0da9 16 : 0dbf 16 0de8 16 : 0df2 16 0df3 16 display position (from left) 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character 1st character 2nd character : 24th character 25th character : 35th character 36th character block block 6 block 7 block 8 block 9 block 10 block 11 block 12 color code 1 specification 0ac0 16 0ac1 16 : 0ad7 16 0ad8 16 : 0ae2 16 0ae3 16 0b40 16 0b41 16 : 0b57 16 0b58 16 : 0b62 16 0b63 16 0bc0 16 0bc1 16 : 0bd7 16 0bd8 16 : 0be2 16 0be3 16 0c40 16 0c41 16 : 0c57 16 0c58 16 : 0c62 16 0c63 16 0cc0 16 0cc1 16 : 0cd7 16 0cd8 16 : 0ce2 16 0ce3 16 0d40 16 0d41 16 : 0d57 16 0d58 16 : 0d62 16 0d63 16 0dc0 16 0dc1 16 : 0dd7 16 0dd8 16 : 0de2 16 0de3 16 character code specification 0a80 16 0a81 16 : 0a97 16 0a98 16 : 0aa2 16 0aa3 16 0b00 16 0b01 16 : 0b17 16 0b18 16 : 0b22 16 0b23 16 0b80 16 0b81 16 : 0b97 16 0b98 16 : 0ba2 16 0ba3 16 0c00 16 0c01 16 : 0c17 16 0c18 16 : 0c22 16 0c23 16 0c80 16 0c81 16 : 0c97 16 0c98 16 : 0ca2 16 0ca3 16 0d00 16 0d01 16 : 0d17 16 0d18 16 : 0d22 16 0d23 16 0d80 16 0d81 16 : 0d97 16 0d98 16 : 0da2 16 0da3 16
67 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 71. ram data for 3nth character 1 1 2 2 3 4 4 5 5 7 6 8 7 10 8 11 9 13 10 14 11 16 12 17 13 19 14 20 15 22 16 23 17 25 18 26 19 28 20 29 21 31 22 32 23 34 24 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536 display sequence ram address order display sequence ram address order 1.5tc size block 1tc size block note: do not read from and write to addresses shown in table 16. table 16. list of access disable addresses 0878 16 08f8 16 0978 16 09f8 16 0a78 16 0af8 16 0b78 16 0bf8 16 0c78 16 0cf8 16 0d78 16 0df8 16 0e78 16 0ef8 16 0f78 16 0ff8 16 0879 16 08f9 16 0979 16 09f9 16 0a79 16 0af9 16 0b79 16 0bf9 16 0c79 16 0cf9 16 0d79 16 0df9 16 0e79 16 0ef9 16 0f79 16 0ff9 16 087a 16 08fa 16 097a 16 09fa 16 0a7a 16 0afa 16 0b7a 16 0bfa 16 0c7a 16 0cfa 16 0d7a 16 0dfa 16 0e7a 16 0efa 16 0f7a 16 0ffa 16
68 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 72. structure of osd ram bit rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 rc10 rc11 rc12 rc13 rc14 rc15 rc16 rc17 rc20 rc21 rc22 rc23 bit name character code (low-order 8 bits) 0 control of character color r control of character color g control of character color b out1 control flash control underline control italic control control of background color r control of background color g control of background color b not used function specification of character code in osd rom 0: color signal output off 1: color signal output on 0: character output 1: background output 0: flash off 1: flash on 0: underline off 1: underline on 0: italic off 1: italic on 0: color signal output off 1: color signal output on bit name character code (low-order 8 bits) 0 control of character color r control of character color g control of character color b out1 control not used control of background color r control of background color g control of background color b not used function specification of character code in osd rom 0: color signal output off 1: color signal output on 0: character output 1: background output 0: color signal output off 1: color signal output on bit name character code (low-order 8 bits) 0 character color code 0 (cc0) character color code 1 (cc1) character color code 2 (cc2) out1 control extra code 0 (ex0) extra code 1 (ex1) extra code 2 (ex2) background color code 0 (bcc0) background color code 1 (bcc1) background color code 2 (bcc2) extra code 3 (ex3) function specification of character code in osd rom specification of character color 0: character output 1: background output specification of extra code in osd rom specification of background color specification of extra code in osd rom cc mode osd mode exosd mode notes 1: read value of bits 4 to 7 of the color code 2 is undefined. 2: for not used bits, the write value is read. 3: set 0 to rc10. b0 rf6 rf5 rf4 rf3 rf2 rf1 rf0 rc17 rc16 rc15 rc14 rc13 rc12 rc11 rc10 rc23 rc22 rc21 rc20 rf7 b3 b0 b7 b0 b7 blocks 1 to16 character code color code 1 color code 2
69 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers b 0 0 0 0 0 1 1 1 g 0 0 1 1 1 1 1 1 r 0 1 0 1 1 1 0 1 table 17. correspondence table of color code 1 and color signal output in exosd mode table 18. correspondence table of color code 2 and color signal output in exosd mode (7) character color the color for each character is displayed by the color code 1. the kinds and specification method of character color are different de- pending on each mode. ? cc mode .................. 7 kinds specified by bits 1 (r), 2 (g), and 3 (b) of color code 1 ? osd mode ............... 7 kinds specified by bits 1 (r), 2 (g) and 3 (b)of color code 1 ? exosd mode .......... 5 kinds specified by bits 1 (cc0), 2 (cc1), and 3 (cc2) of color code 1 the correspondence table of color code 1 and color signal output in the exosd mode is shown in table 17. (8) character background color the character background color can be displayed in the character display area. the character background color for each character is specified by color code 2. the kinds and specification method of char- acter background color are different depending on each mode. ? cc mode .................. 7 kinds specified by bits 0 (r), 1 (g), and 2 (b) of color code 2 ? osd mode ............... 7 kinds specified by bits 0 (r), 1 (g), and 2 (b) of color code 2 ? exosd mode .......... 5 kinds specified by bits 0 (bcc0), 1 (bcc1), and 2 (bcc2) of color code 2 the correspondence table of the color code 2 and color signal output in the exosd mode is shown in table 18. note : the character background color is displayed in the following part : (character display area)C(character font)C(border)C(extra font). accordingly, the character background color does not mix with these color signal. bit 3 cc2 0 0 0 0 1 1 1 1 bit 2 cc1 0 0 1 1 0 0 1 1 bit 1 cc0 0 1 0 1 0 1 0 1 r 0 1 0 1 1 1 0 1 g 0 0 1 1 1 1 1 1 color code 1 bit 2 bcc2 0 0 0 0 1 1 1 1 bit 1 bcc1 0 0 1 1 0 0 1 1 bit 0 bcc0 0 1 0 1 0 1 0 1 color code 2 color signal output color signal output b 0 0 0 0 0 1 1 1
70 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (9) out1, out2 signals the out1, out2 signals are used to control the luminance of the video signal. the output waveform of the out1, out2 signals is controlled by bit 4 of color code 1 (refer to figure 72), bits 2 and 7 of fig. 73. setting value for controlling out1, out2 and corresponding output waveform the block control register (refer to figure 56). the setting values for controlling out1, out2 and the corresponding output waveform is shown in figure 73. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 block control register out2 output control bit (b7) border output control bit (b2) output waveform out1 control (b4 of color code 1)
71 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (10) attribute the attributes (flash, underline, italic) are controlled to the character font. the attributes for each character are specified by the color codes 1 and 2 (refer to figure 71). the attributes to be controlled are differ- ent depending on each mode. cc mode ..................... flash, underline, italic osd mode .................. border (all bordered, shadow bordered can be selected) exosd mode ............. border (all bordered, shadow bordered can be selected) , extra font (16 kinds) under line the underline is output at the 23th and 24th dots in vertical direction only in the cc mode. the underline is controlled by bit 6 of color code 1. the color of underline is the same color as that of the charac- ter font. flash the parts of the character font, the underline, and the character back- ground are flashed only in the cc mode. the color signals (r, g, b, out1) of the character font and the underline are controlled by bit 5 of color code 1. all of the color signals for the character font flash. however, the color signal for the character background can be con- trolled by bit 3 of the osd control register (refer to figure 52). the flash cycle bases on the v sync count. v sync cycle 5 48 800 ms (at flash on) v sync cycle 5 16 267 ms (at flash off) italic the italic is made by slanting the font stored in osd rom to the right only in the cc mode. the italic is controlled by bit 7 of color code 1. the display example of the italic and underline is shown in figure 75. in this case, r is displayed. notes 1: when setting both the italic and the flash, the italic charac- ter flashes. 2: when the pre-divide ratio = 1, the italic character with slant of 1 dot 5 5 steps is displayed (refer to figure 74 (c)). when the pre-divide ratio = 2, the italic character with slant of 1/2 dot 5 10 steps is displayed (refer to figure 74 (d)). 3: the boundary of character color is displayed in italic. how- ever, the boundary of character background color is not af- fected by the italic (refer to figure 75). 4: the adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to figure 75). 5: when displaying the italic character in the block with the pre-divide ratio = 1, set the osd clock frequency to 11 mhz to 14 mhz. a
72 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 75. example of italic display fig. 74. example of attribute display (in cc mode) 0 0 10 0 1 0 1 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 (a) ordinary (b) underline (c) italic (pre-divide ratio = 1) (d) italic (pre-divide ratio = 2) 10 0 1 1 0 1 italic on one side italic on both sides bit 7 of color code 1 note : the wavy-lined is the boundary of character color
73 single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers extra font there are 16 kinds of the extra fonts configured with 16 5 26 dots in osd rom. this 16 kinds fonts can be displayed by ored with t he character font by a character unit (refer to figure 53). in only the exosd mode, the extra font is controlled the following : bit s 7 to 5 of the color code 1 and bit 3 of the color code 2. the extra font color for each screen is specified by the ext ra color register. when the character font overlaps with the extra fo nt, the color of the area becomes the ored color of both fonts. notes 1 : when using the extra font, set bits 7 and 6 of the osd control register to 0 (refer to figure 55). 2 : extra fonts are always displayed by ored with the char- acter font. accordingly, when displaying only a extra font, set a blank for a character font and or with it. fig. 76. extra font color register fig. 77. display example of only extra font 7 extra font color register (ec : address 0219 16 ) extra font color r control bit 0 : no output 1 : output extra font color g control bit 0 : no output 1 : output extra font color b control bit 0 : no output 1 : output fix these bits to 0. 00 16 dots 20 dots 16 dots 26 dots 16 dots 26 dots + (or) extra font specified by ex0 to ex3 blank character font 0
74 single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers border the border is output in the osd mode and the exosd mode. the all bordered (bordering around of character font) and the shadow bor- dered (bordering right and bottom sides of character font) a re se- lected (refer to figure 77) by bit 2 of the osd control regi ster (refer to figure 55). the border on/off is controlled by bit 2 of the block control register (refer to figure 56). the out1 signal is used for border output. the border color for each screen is specified by the border color register. the horizontal size (x) of border is 1t c (osd clock cycle divided in the pre-divide circuit) regardless of the character font dot size. how- ever, only when the pre-divide ratio = 2 and character size = 1.5t c , the horizontal size is 1.5t c . the vertical size (y) different depending on the screen scan mode and the vertical dot size of charact er font. notes 1 : there is no border for the extra font. 2 : the border dot area is the shaded area as shown in figure 79. in the exosd mode, top and bottom of character font display area is not bordered. 3 : when the border dot overlaps on the next character font, the character font has priority (refer to figure 80 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 80 b). 4 : the border is not displayed at right side of the most right dot in the display area of the 36th character (the character located at the most right of the block). however, note that eprom version can display the bor- der above when programming. (the border for the right edge dots of the 40ths character area is not displayed.) fig. 78. example of border display fig. 79. horizontal and vertical size of border all bordered shadow bordered y x 1/2h 1h, 2h, 3h 1/2h, 1h, 2h, 3h 1/2h 1h 1h vertical dot size of character font border dot size scan mode horizontal size (x) vertical size (y) normal scan mode bi-scan mode 1t c (osd clock cycle divided in pre-divide circuit) 1.5t c when selecting 1.5t c for character size.
75 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 80. border area fig. 81. border priority fig. 82. border color register 16 dots 16 dots character font area 20 dots osd mode exosd mode 1 dot width of border 1 dot width of border 1 dot width of border 1 dot width of border character font area 20 dots character boundary b character boundary a character boundary b 7 border color register (fc : address 021b 16 ) border color r control bit 0 : no output 1 : output border color g control bit 0 : no output 1 : output border color b control bit 0 : no output 1 : output fix these bits to 0. 00 0
76 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (11) multiline display the m37274ma-xxxsp can ordinarily display 16 lines on the crt screen by displaying 16 blocks at different vertical positions. in addi- tion, it can display up to 12 lines by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. the mode in which an osd interrupt occurs is different depending on the setting of the raster color regis- ter (refer to figure 89). ? when bit 7 of the raster color register is 0 an osd interrupt occurs at the end of block display in the osd and the exosd mode. ? when bit 7 of the raster color register is 1 an osd interrupt occurs at the end of block display in the cc mode. notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control reg- ister (addresses 00d0 16 to 00db 16 ), an osd interrupt re- quest does not occur (refer to figure 83 (a)). 2: when another block display appeares while one block is displayed, an osd interrupt request occurs only once at the end of the another block display (refer to figure 83 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the cc mode block (off display) out of window (refer to figure 83 (c)). fig. 83. note on occurence of osd interrupt (b) (c) block 1 (on display) block 2 (on display) block 3 (on display) block 4 (on display) block 1 (on display) block 2 (on display) block 3 (off display) block 4 (off display) osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request no osd interrupt request block 1 block 2 osd interrupt request osd interrupt request osd interrupt request osd interrupt request block 1 block 2 block 3 on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) in cc mode window no osd interrupt request no osd interrupt request (a)
77 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers bit 4 of osd control register bit 7 of block control register bit 4 of color code 1 out1 output signal out2 output signal note : when using this function, set 09 16 to the character below : the 1st character the 34th character and the following character. (12) automatic solid space function this function generates automatically the solid space (out1 or out2 blank output) of the character area in the cc mode. the solid space is output in the following area : the character area except character code 09 16 the character area on the left and right sides this function is turned on and off by bit 4 of the osd control register (refer to figure 55). 0 01 character character font part display area off table 19. setting for automatic solid space 0 1 01 character font part off character display area 0 01 solid space off 1 1 01 character font part solid space fig. 84. display screen example of automatic solid space 09 05 09 09 09 06 06 16 16 16 16 16 16 16 06 09 16 16 ? ? ? ? ? ? 09 16 09 16 when setting the character code 05 16 as the character a, 06 16 as the character b. (osd ram) character to be displayed (display screen) 2nd character 3rd character ( see note 1 ) no blank output 34th character 35th character 36th character ( see note 1 ) 1st character
78 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (13) scan mode m37271mf-xxxsp has the bi-scan mode for corresponding to h sync of double speed frequency. in the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. the scan mode is selected by bit 1 of the osd control register (refer to figure 55). (14) window function this function sets the top and bottom boundary of display limit on a screen. the window function is valid only in the cc mode. the top boundary is set by window h registers 1 and 2. the bottom bound- ary is set by window l registers 1 and 2. this function is turned on and off by bit 5 of the osd control register (refer to figure 55). the structure of window h registers 1 and 2 is shown in figure 86, the structure of window l registers 1 and 2 is shown in figure 87. notes 1: set values except 00 16 and 01 16 to the window h regis- ter 1 when the window h register 2 is 00 16 . 2: set the register value fit for the following condition : (wh1 + wh2) < (wl1 + wl2) bit 1 of osd control register vertical display start position vertical dot size table 20. setting for scan mode normal scan 0 value of vertical position register 5 1h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h bi-scan 1 value of vertical position register 5 2h 1t c 5 1h 1t c 5 2h 2t c 5 4h 3t c 5 6h scan mode parameter fig. 85. example of window function exosd mode window fgh ij cc mode kl mno cc mode pqrst cc mode osd mode bottom boundary of window top boundary of window screen abcde uvwxy
79 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 87. window l registers fig. 86. window h registers 7 7 window l register 1 (wl1 : address 021d 16 ) control bits of window bottom boundary (note) bottom boundary position (low-order 8bits) t h 5 (setting value of low-order 2bits of wl2 5 16 + setting value of high-order 4bits of wl1 5 16 + setting value of low-order 4bits of wl1 5 16 ) 2 0 1 window l register 2 (wl2 : address 021f 16 ) control bits of window bottom boundary (note) bottom boundary position (high-order 2bits) t h 5 (setting value of low-order 2bits of wl2 5 16 + setting value of high-order 4bits of wl1 5 16 + setting value of low-order 4bits of wl1 5 16 ) 2 0 1 note : set values fit for the following condition : (wh1 + wh2) < (wl1 + wl2). 7 7 window h register 1 (wh1 : address 021c 16 ) control bits of window top boundary (note) top boundary position (low-order 8bits) t h 5 (setting value of low-order 2bits of wh2 5 16 + setting value of high-order 4bits of wh1 5 16 + setting value of low-order 4bits of wh1 5 16 ) 2 0 1 window h register 2 (wh2 : address 021e 16 ) control bits of window top boundary (note) top boundary position (high-order 2bits) t h 5 (setting value of low-order 2bits of wh2 5 16 + setting value of high-order 4bits of wh1 5 16 + setting value of low-order 4bits of wh1 5 16 ) 2 0 1 note : set values except 00 16 and 01 16 to the wh1 when the wh2 is 00 16. 0 0 0 0
80 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (15) osd output pin control the osd output pins r, g, b, and out1 can also function as ports p5 2 , p5 3 , p5 4 and p5 5 . set the corresponding bit of the osd port control register (address 00cb 16 ) to 0 to specify these pins as osd output pins, or set it to 1 to specify it as a general-purpose port p5 pins. the out2 can also function as port p1 0 . set the corresponding bit of the port p1 direction register (address 00c3 16 ) to 1 (output mode). after that, switch between the osd output function and the port function by the osd port control register. set the corresponding bit to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 pin. the input polarity of the h sync , v sync and output polarity of signals r, g, b, out1 and out2 can be specified with the i/o polarity con- trol register (address 0217 16 ) . set a bit to 0 to specify positive polarity; set it to 1 to specify negative polarity (refer to figure 68). the osd port control register is shown in figure 88. fig. 88. osd port control register 70 0 osd port control register (pf : address 00cb 16 ) fix these bits to ?. port p5 2 output signal selection bit 0 : r signal output 1 : port p5 2 output port p5 3 output signal selection bit 0 : g signal output 1 : port p5 3 output port p5 4 output signal selection bit 0 : b signal output 1 : port p5 4 output port p5 5 output signal selection bit 0 : out1 signal output 1 : port p5 5 output port p1 0 output signal selection bit 0 : port p1 0 output 1 : out2 signal output fix this bit to ?. 00
81 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers (16) raster coloring function an entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 7 raster colors can be obtained. if the out1 pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. this setting is necessary for erasing a background tv image. if the r, g, and b pins have been set to output, a raster coloring signal is output in the part except a no-raster colored character (in figure 90, a character 1) and the character background output dur- ing 1 horizontal scanning period. this ensures that the character color/ the character background color is not mixed with the raster color. the structure of the raster color register is shown in figure 89, the example of raster coloring is shown in figure 90. fig. 89. raster color register fig. 90. example of raster coloring 7 raster color register (rc : address 0218 16 ) raster color r control bit 0 : no output 1 : output raster color g control bit 0 : no output 1 : output raster color b control bit 0 : no output 1 : output raster color i1 control bit 0 : no output 1 : output raster color out2 control bit 0 : no output 1 : output osd interrupt source selection bit 0 : interrupt occurs at end of osd or exosd block display 1 : interrupt occurs at end of cc mode block display h sync a' a out1 r g b : character color red (r) : border color green (g) : background color magenta (r and b) : raster color blue (b and out1) signals across a-a' 0
82 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 92. rom correction enable register fig. 91. rom correction address registers rom correction function this can correct program data in rom. up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the rom cor- rection memory in ram. the rom memory for correction is 32 bytes 5 2 blocks. block 1 : addresses 02c0 16 to 02df 16 block 2 : addresses 02e0 16 to 02ff 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction address, the main pro- gram branches to the correction program stored in the rom memory for correction. to return from the correction program to the main pro- gram, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. when the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. the rom correction function is controlled by the rom correction enable register. notes 1 : specify the first address (op code address) of each instruction as the rom correction address. 2 : use the jmp instruction (total of 3 bytes) to return from the main program to the correction program. 3 : do not set the same rom correction address to blocks 1 and 2. 0242 16 rom correction address 1 (high-order) 0243 16 rom correction address 1 (low-order) 0244 16 rom correction address 2 (high-order) 0245 16 rom correction address 2 (low-order) 0 0 7 fix these bits to 0. rom correction enable register (rcr : address 0246 16 ) 0 0 : disabled 1 : enabled 0 : disabled 1 : enabled block 1 enable bit block 2 enable bit
83 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the ______ reset pin at low for 2 m s or more, then return is to high. then, as shown in figure 94, reset is released and the program starts form the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figures 5 to 9. an example of the reset circuit is shown in figure 93. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig. 94. reset sequence fig. 93. example of reset circuit power source voltage 0 v reset input voltage 0 v 4.5 v 0.9 v poweron 26 30 27 vcc reset vss m37274ma-xxxsp 1 5 4 3 0.1 m f m51953al x in f reset internal reset sync address data 32768 count of x in clock cycle (note 3) reset address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff ad h , ad l ? ? ? ? ? ad l ad h notes 1 : f(x in ) and f( ) are in the relation : f(x in ) = 2f ( f ). 2: a question mark (?) indicates an undefined state that depends on the previous state. 3 : immediately after a reset, timer 3 and timer 4 are connected by hardware. at this time, ff 16 is set in timer 3 and 07 16 is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal.
84 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers clock generating circuit the m37274ma-xxxsp has 2 built-in oscillation circuits. an oscilla- tion circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no exter- nal resistor is needed between x in and x out since a feed-back re- sistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . when using x cin -x cout as sub- clock, clear bits 5 and 4 of the clock source control register to 0. to supply a clock signal externally, input it to the x in (x cin ) pin and make the x out (x cout ) pin open. when not using x cin clock, con- nect the x cin to v ss and make the x cout pin open. after reset has completed, the internal clock f is half the frequency of x in . immediately after poweron, both the x in and x cin clock start oscillating. to set the internal clock f to low-speed operation mode, set bit 7 of the cpu mode register (address 00fb 16 ) to 1. oscillation control (1) stop mode the built-in clock generating circuit is shown in figure 95. when the stp instruction is executed, the internal clock f stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in timer 4. select f(x in )/16 or f(x cin )/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00c7 16 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before execution of the stp instruction. the oscillator restarts when external interrupt is accepted. however, the internal clock f keeps its h level until timer 4 overflows, allow- ing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) wait mode when the wit instruction is executed, the internal clock f stops in the h level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (note). since the oscillator does not stop, the next instruction can be executed at once. note: in the wait mode, the following interrupts are invalid. (1) v sync interrupt (2) osd interrupt (3) timers 1 and 2 interrupts using tim2 pin input as count source (4) timer 3 interrupt using tim3 pin input as count source (5) data slicer interrupt (6) multi-master i 2 c-bus interface interrupt (7) f(x in )/4096 interrupt (8) all timer interrupts using f(x in )/2 or f(x cin )/2 as count source (9) all timer interrupts using f(x in )/4096 or f(x cin )/4096 as count source (10) a-d conversion interrupt fig. 95. ceramic resonator circuit example fig. 96. external clock input circuit example (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm 6 ) of the cpu mode register (00fb 16 ) to 1. when the main clock x in is restarted, the program must allow enough time to for oscillation to stabilize. note that in low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption. to reduce the x cin -x cout drivability, clear bit 5 (cm 5 ) of the cpu mode regis- ter (00fb 16 ) to 0. at reset, this bit is set to 1 and strong drivability is selected to help the oscillation to start. when an stp instruction is executed, set this bit to 1 by software before executing. x cin x in c cin m37274ma-xxxsp x cout r f r d c cout x out c in c out x cin m37274ma-xxxsp external oscillation circuit or external pulse x cout x in x out open open external oscillation circuit vcc vss vcc vss
85 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 97. clock generating circuit block diagram x cin x cout osc1 oscillating mode selection bits (notes 1, 4) internal system clock selection bit (notes 1, 3) internal system clock selection bit (notes 1, 3) main clock (x in Cx out ) stop bit (notes 1, 3) r s q stp instruction wit instruction r s q reset interrupt disable flag i interrupt request r s q reset stp instruction timing (internal clock) timer 3 count source selection bit (notes 1, 2) 1 timer 3 count stop bit (notes 1, 2) timer 4 count stop bit (notes 1, 2) timer 3 timer 4 1/2 1/8 x out x in 1 0 0 notes 1 : the value at reset is 0. 2 : refer to the structure of timer mode register 2. 3 : refer to the structure of cpu mode register (next page). 4 : refer to the structure of clock source control register.
86 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers fig. 98. state transitions of system clock reset the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. the f indicates the internal clock. wit instruction cm7 : internal system clock selection bit 0 : x in -x out selected (high-speed mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (address : 00fb 16 ) cm6 : main clock (x in ? out ) stop bit 0 : oscillating 1 : stopped 8mhz oscillating 32khz oscillating f is stopped (high) timer operating 8mhz oscillating 32khz oscillating f( f ) = 4mhz 8mhz stopped 32khz stopped f is stopped (high) 8mhz oscillating 32khz oscillating f is stopped (high) timer operating (note 3) 8mhz oscillating 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz stopped f is stopped (high) 8mhz stopped 32khz stopped f = stopped (high ) 8mhz stopped 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz oscillating f is stopped (high) timer operating (note 3) interrupt stp instruction interrupt (note 1) wit instruction interrupt wit instruction interrupt stp instruction interrupt (note 2) stp instruction interrupt (note 2) cm7 = 1 cm7 = 0 cm6 = 1 cm6 = 0 external int, timer interrupt, or si/o interrupt external int notes 1: when the stp state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: the delay after the stp state ends is approximately 2s. 3: when the internal clock f divided by 8 is used as the timer count source, the frequency of the count source is 2khz. the program must allow time for 8mhz oscillation to stabilize high-speed operation start mode
87 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 0216 16 ). addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740
88 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers i ol2 i ol3 i ol4 f(x in ) f(x cin ) 7.9 29 11.0 26.5 15.262 1.5 input frequency tim2, tim3, int1, int2, int3 input frequency s clk input frequency scl1, scl2 input frequency horizontal sync. signal of video signal input amplitude video signal cv in oscillation frequency (for osd) osc1 power source voltagev cc , av cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 4 , p6 3 , p7 0 Cp7 2 , x in , h sync , v sync , ______ reset output voltage p0 3 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p5 2 Cp5 5 , s out , s clk , x out , osc2 output voltage p0 0 Cp0 2 , p0 4 Cp0 7 circuit current p5 2 Cp5 5 , p1 0 , p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 circuit current p5 2 Cp5 5 , p1 0 , , p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , s out , s clk circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 2 , p0 4 Cp0 7 circuit current p3 0 , p3 1 power dissipation operating temperature storage temperature v o i oh i ol1 i ol2 i ol3 limits symbol v cc , av cc v i v i v o absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. parameter C0.3 to 13 0 to 1 (note 1) 0 to 2 (note 2) 0 to 6 (note 2) 0 to 1 (note 2) 0 to 10 (note 3) 550 C10 to 70 C40 to 125 v ma ma ma ma ma mw c c min. 4.5 2.0 0 0.8v cc 0.7v cc 0 0 0 typ. 5.0 0 max. 5.5 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 v v v v v v v v ma ma recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) power source voltage (note 4), during cpu, osd, data slicer operation ram hold voltage (when clock is stopped) power source voltage high input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p4 0 Cp4 6 , p6 4 , p7 0 Cp7 2 , h sync , v sync , ______ reset, x in , p6 3 high input voltage scl1, scl2, sda1, sda2 low input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p4 0 Cp4 6 , p6 3 , p6 4 , p7 0 Cp7 2 low input voltage scl1, scl2, sda1, sda2 low input voltage (note 6) ______ reset, x in , osc1, h sync , v sync , int1, int2, int3, tim2, tim3, s clk , s in high average output current (note 1) p5 2 Cp5 5 , p1 0 , p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low average output current (note 2) p5 2 Cp5 5 , p1 0 , p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , s out , s clk low average output current (note 2) p1 1 Cp1 4 low average output current (note 2) p0 0 Cp0 2 , p0 4 Cp0 7 low average output current (note 3) p3 0 , p3 1 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for sub-clock operation) x cin v cc , av cc v cc , av cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 symbol parameter unit f hs1 f hs2 f hs3 f hs4 v i khz mhz khz khz v mhz ma ma ma mhz khz 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5 8.0 32 27.0 15.734 2.0 i ol4 p d t opr t stg f osc lc oscillating mode ceramic oscillating mode t a = 25 c unit v v v v ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3
89 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers power source current high output voltage p5 2 Cp5 5 , p1 0 , p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low output voltage p5 2 Cp5 5 , p1 0 , s out , s clk , p0 0 Cp0 7 , p1 5 Cp1 7 , p2 0 Cp2 7 low output voltage p3 0 , p3 1 low output voltage p1 1 Cp1 4 hysteresis (note 6) ______ reset, h sync , v sync , int1, int2, int3, tim2, tim3, s in , s clk , scl1, scl2, sda1, sda2 high input leak current ______ reset, p0 3 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 3 , p6 4 , p7 0 Cp7 2 , h sync , v sync high input leak current p0 0 Cp0 2 , p0 4 Cp0 7 low input leak current ______ reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 C p2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 3 , p6 4 , p7 0 Cp7 2 , h sync , v sync i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v i ol = 3 ma i ol = 6 ma v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 12 v v cc = 5.5 v v i = 0 v v cc = 4.5 v ma m a ma m a v v max. 30 50 200 4 100 10 0.4 limits min. 2.4 electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) i cc v oh v ol typ. 15 30 60 2 25 1 symbol parameter test conditions unit wait mode stop mode system operation v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, osd off, data slicer off, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma crt off data slicer off crt on data slicer on v cc = 5.5 v, f(x in ) = 8 mhz 0.5 3.0 0.4 0.6 1.3 5 10 5 130 v t+ Cv tC i izh i izl r bs v m a m a w notes 1: the total current that flows out of the ic must be 20 or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 20 ma or less. 3: the total average input current for ports p3 0 , p3 1 to ic must be 10 ma or less. 4: connect 0.1 m f or more capacitor externally between the power source pins v cc Cv ss and av cc Cv ss so as to reduce power source noise. also connect 0.1 m f or more capacitor externally between the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p1 6 , p4 1 Cp4 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p1 7 and p4 6 have the hysteresis when these pins are used as serial i/o pins. 7: when using the sub-clock, set f clk < f cpu /3. 8: pin names in each parameter is described as below. (1) dedicated pins: dedicated pin names. (2) duble-/triple-function ports ? when the same limits: i/o port name. ? when the limits of functins except ports are different from i/o port limits: function pin name.
90 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers a-d converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) resolution non-linearity error differential non-linearity error zero transition error full-scale transition error conversion time reference voltage ladder resistor analog input current max. 8 2 0.9 2 4 12.5 v cc v ref bits lsb lsb lsb lsb m s v k w v min. 0 0 0 0 12.25 0 limits typ. unit test conditions parameter symbol v ot v fst t conv v ref r ladder v ia v cc = 5.12v i ol (sum) = 0ma v cc = 5.12v 25 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta t su:sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig. 101. definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd : sta t low t r t hd : dat t high t f t su : dat t su : sta sr p t su : sto t hd : sta s sr p : start condition : restart condition : stop condition
91 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers package outline
92 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers gzzCsh11C19b < 69a0 > 740 family mask rom confirmation form single-chip microcomputer m37274ma-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 00000 16 product name ascii code : m37274ma C 0000f 16 0ffff 16 set ff 16 in the shaded area and in the addresses at which osd rom data does not present (refer to page 4/4). write the ascii codes that indicates the product name of m37274maC to addresses 00000 16 to 0000f 16 . (1) eprom type (indicate the type used) 06000 16 rom (40 k) 1ffff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52p4b for m37274ma-xxxsp) and attach to the mask rom confirmation form. (1/4) do you set ff 16 in the shaded areaand in the addresses at which osd rom data does not present (refer to page 4/4)? do you write the ascii codes that indicates the product name of m37274maC to addresses 00000 16 to 0000f 16 ? eprom data check item (refer the eprom data and check in the appropriate box) ? yes ? yes ? ? 10800 16 osd rom 1e41f 16 (2)
93 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers gzz?h11?9b < 69a0 > 740 family mask rom confirmation form single-chip microcomputer m37274ma-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 37 16 ? = 3 4 16 ? = 4d 16 ? = 41 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 00000 16 to 0000f 16 store the product name, and addresses 10800 16 to 1ffff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37274ma-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data to character rom. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/4)
94 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers gzzCsh11C19b < 69a0> series melps 740 mask rom confirmation form single-chip microcomputer m37274ma-xxxsp mitsubishi electric mask rom number font data must be stored in the proper osd rom address according to the following table. (3/4) (2)osd rom address of extra font data (1)osd rom address of character font data line number = 02 16 to 15 16 character code = 00 16 to ff 16 font bit = 0 : left font 1 : right font osd rom address bit line number / character code / font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 10 font bit line number character code osd rom address bit line number / extra code / font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 11 font bit line number extra code 0000 example) the font data 60 (shaded area ) of the character code aa 16 is stored in address 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 2 =12954 16 . 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 12 16 13 16 14 16 15 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 left font right font line number (1) character code aa 16 line number 19 16 (2) extra code 0a 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 left font right font 00 16 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 line number = 00 16 to 19 16 extra code = 00 16 to 0f 16 font bit = 0 : left font 1 : right font example) the font data 03 (shaded area ) of the extra code 0a 16 is stored in address 1 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 2 =1d415 16 . 0
95 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers gzz?h11?9b < 69a0 > 740 family mask rom confirmation form single-chip microcomputer m37274ma-xxxsp mitsubishi electric (4/4) 10a00 16 to 10bff 16 10e00 16 to 10fff 16 11200 16 to 113ff 16 11600 16 to 117ff 16 11a00 16 to 11bff 16 11e00 16 to 11fff 16 12200 16 to 123ff 16 12600 16 to 127ff 16 12a00 16 to 12bff 16 12e00 16 to 12fff 16 13200 16 to 133ff 16 13600 16 to 137ff 16 13a00 16 to 13bff 16 13e00 16 to 13fff 16 14200 16 to 143ff 16 14600 16 to 147ff 16 14a00 16 to 14bff 16 14e00 16 to 14fff 16 15200 16 to 153ff 16 15600 16 to 17fff 16 18020 16 to 183ff 16 18420 16 to 187ff 16 18820 16 to 18bff 16 18c20 16 to 18fff 16 19020 16 to 193ff 16 19420 16 to 197ff 16 19820 16 to 19bff 16 19c20 16 to 19fff 16 1a020 16 to 1a3ff 16 1a420 16 to 1a7ff 16 1a820 16 to 1abff 16 1ac20 16 to 1afff 16 1b020 16 to 1b3ff 16 1b420 16 to 1b7ff 16 1b820 16 to 1bbff 16 1bc20 16 to 1bfff 16 1c020 16 to 1c3ff 16 1c420 16 to 1c7ff 16 1c820 16 to 1cbff 16 1cc20 16 to 1cfff 16 1d020 16 to 1d3ff 16 1d420 16 to 1d7ff 16 1d820 16 to 1dbff 16 1dc20 16 to 1dfff 16 1e020 16 to 1e3ff 16 the following osd rom addresses must be set ?f.?there are no font data in these addresses.
96 single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. mitsubishi microcomputers
97 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. appendix pin configuration (top view) outline 52p4b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 hlf/ad6 h sync v sync p4 0 /ad4 p4 1 /int2 p4 2 /tim2 p4 3 /tim3 p2 4 /ad3 p2 5 /ad2 p0 1 /pwm5 p0 2 /pwm6 p1 7 /s in p4 4 /int1 p4 6 /s clk av cc p7 2 /rvco p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p0 4 /pwm0 p0 5 /pwm1 p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 p1 6 /int3 p3 0 p3 1 reset p6 4 /osc2/x cout p6 3 /osc1/x cin v cc p0 3 /da p2 6 /ad1 p2 7 /ad5 p0 0 /pwm4 p4 5 /s out p0 6 /pwm2 p2 1 p2 2 p2 3 17 18 19 20 37 36 35 34 33 m37274ma-xxxsp p7 0 /cv in p7 1 /v hold cnv ss x out x in v ss 21 22 23 24 25 26 32 31 30 29 28 27 p0 7 /pwm3 p2 0
98 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. memory map 0000 16 00c0 16 00ff 16 0df3 16 sfr1 area not used ffff 16 ffde 16 ff00 16 0800 16 interrupt vector area not used 10800 16 1ffff 16 special page rom (40 k bytes) ram for osd (note) (1296 bytes) ram (768 bytes) zero page 0200 16 0248 16 6000 16 sfr2 area not used 0300 16 not used 155ff 16 18000 16 not used 1e41f 16 10000 16 rom for osd (11072 bytes) 043f 16 not used note : refer to table 15. contents of osd ram. 02c0 16 02ff 16 rom correction memory block 1 : addresses 02c0 16 to 02df 16 block 2 : addresses 02e0 16 to 02ff 16
99 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. memory map of special function register (sfr) n sfr1 area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) osd control register (oc) horizontal position register (hp) block control register 1 (bc 1 ) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) block control register 2 (bc 2 ) block control register 3 (bc 3 ) block control register 4 (bc 4 ) block control register 5 (bc 5 ) block control register 6 (bc 6 ) block control register 7 (bc 7 ) b7 b0 bit allocation state immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? ? ? ? ? ? port p4 (p4) port p4 direction register (d4) osd port control register (pf) port p6 (p6) block control register 8 (bc 8 ) block control register 9 (bc 9 ) block control register 10 (bc 10 ) block control register 11 (bc 11 ) block control register 12 (bc 12 ) r0 0 g b out1 out2 0 0? 0 0? ? 0 ? ? ? ? ? ? ? oc6 oc7 oc4 oc5 oc2 oc3 oc0 oc1 00 16 bc 1 1 bc 1 2 bc 1 3 bc 1 4 bc 1 5 bc 1 6 bc 1 7 bc 1 8 bc 2 1 bc 2 2 bc 2 3 bc 2 4 bc 2 5 bc 2 6 bc 2 7 bc 2 8 bc 3 1 bc 3 2 bc 3 3 bc 3 4 bc 3 5 bc 3 6 bc 3 7 bc 3 8 bc 4 1 bc 4 2 bc 4 3 bc 4 4 bc 4 5 bc 4 6 bc 4 7 bc 4 8 bc 5 1 bc 5 2 bc 5 3 bc 5 4 bc 5 5 bc 5 6 bc 5 7 bc 5 8 bc 6 1 bc 6 2 bc 6 3 bc 6 4 bc 6 5 bc 6 6 bc 6 7 bc 6 8 bc 7 1 bc 7 2 bc 7 3 bc 7 4 bc 7 5 bc 7 6 bc 7 7 bc 7 8 bc 8 1 bc 8 2 bc 8 3 bc 8 4 bc 8 5 bc 8 6 bc 8 7 bc 8 8 bc 9 1 bc 9 2 bc 9 3 bc 9 4 bc 9 5 bc 9 6 bc 9 7 bc 9 8 bc 10 1 bc 10 2 bc 10 3 bc 10 4 bc 10 5 bc 10 6 bc 10 7 bc 10 8 bc 11 1 bc 11 2 bc 11 3 bc 11 4 bc 11 5 bc 11 6 bc 11 7 bc 11 8 bc 12 1 bc 12 2 bc 12 3 bc 12 4 bc 12 5 bc 12 6 bc 12 7 bc 12 8 hp6 hp7 hp4 hp5 hp2 hp3 hp0 hp1 00 16 0 0 00 16 ? 00 16 ? 00 16 ? port p7 (p7) : fix to this bit to 0 (do not write to 1) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 t3sc
100 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 data slicer control register 1 (dsc1) data register 3 (cd3) a-d conversion register (ad) a-d control register (adcon) timer 1 (tm1) window register (wn) clock run-in register 1 (cr1) clock run-in register 2 (cr2) data register 1 (cd1) data register 2 (cd2) caption position register (cp) start bit position register (sp) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer mode register 1 (tm1) timer mode register 2 (tm2) i 2 c data shift register (s0) i 2 c control register (s1d) i 2 c clock control register (s2) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) clock run-in detect register 1 (crd1) clock run-in detect register 2 (crd2) data register 4 (cd4) cpu mode register (cpum) b7 b0 adin0 adin1 advref adstr tm20 tm21 tm22 tm23 tm24 tm10 tm11 tm12 tm13 tm14 cm2 tm1r tm2r tm3r tm4r crtr vscr adr ck0 int1r dsr sior tm1e tm2e tm3e tm4e crte vsce int1e dse sioe int2e tm25 b7 b0 00 16 ?0 0100 0 0 ff 16 07 16 ff 16 07 16 1 0 0 11 1 00 sync slice register (ssl) data slicer control register 2 (dsc2) i 2 c status register (s1) i 2 c address register (s0d) ? 0? 00 0 ? 0 00 16 ? tm15 tm16 tm17 tm26 tm27 ? sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack 00 16 00 16 00 16 0 0 00 0 1? 0 1msr int2r iicr t56r ade 1mse iice t56e t56s cm7 cm5 cm6 dsc20 dsc21 dsc22 dsc25 dsc27 dsc10 dsc11 dsc12 dsc15 dsc17 ssl7 cp0 cp1 cp2 cp3 cp4 sp0 sp1 sp2 sp3 sp4 sp5 sp6 sp7 wn0 wn1 wn2 wn3 wn4 wn5 crd20 crd21 crd22 crd25 crd27 crd25 crd25 crd25 cr21 cr11 crd15 crd17 crd15 crd15 crd15 sfr1 area (addresses e0 16 to ff 16 ) address register bit allocation state immediately after reset 100 00 00 0 11 00 100111 1 0101 000 000 0 0 11 0 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 : fix to this bit to 0 (do not write to 1) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 cr13 cr12 cr10 adin2 ? 0? 00 0 0 0 00 16
101 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 21a 16 21b 16 21c 16 21d 16 21e 16 21f 16 200 16 201 16 202 16 203 16 204 16 205 16 206 16 207 16 208 16 209 16 20b 16 20c 16 20d 16 20e 16 20f 16 20a 16 pwm mode register 1 (pn) timer 5 (tm5) sync pulse counter register (syc) data slicer control register 3 (dsc3) pwm2 register (pwm2) pwm6 register (pwm6) pwm4 register (pwm4) pwm5 register (pwm5) pwm0 register (pwm0) pwm1 register (pwm1) interrupt input polarity register (ip) serial i/o mode register (sm) serial i/o register (sio) clock source control register (cs) extra font color register (ec) window h register 1 (wh1) window l register 1 (wh1) window h register 2 (wh2) window l register 2 (wh2) clock run-in detect register 3 (crd3) clock run-in register (cr3) timer 6 (tm6) border color register (fc) b7 b0 syc0 fc2 b7 b0 00 16 pwm3 register (pwm3) pwm mode register 2 (pw) raster color register (rc) i/o polarity control register (pc) ? ? ? ? ? ? ? ff 16 00 16 00 16 pw0 pw1 pw2 pw3 pw4 pw5 pw6 pn3 syc1 syc2 syc3 syc4 syc5 dsc30 dsc31 dsc32 dsc37 dsc35 re1 re2 re5 int3 pol ad/int3 sel int3 pol ad/int3 sel sm0 re1 re2 re3 sm4 re5 int3 pol ad/int3 sel sm1 sm2 sm3 sm5 pc0 re1 re2 re3 pc4 re5 int3 pol ad/int3 sel pc1 pc2 pc5 pc6 pc7 re1 re2 re3 re5 int3 pol ad/int3 sel cs0 cs4 cs1 cs2 cs3 cs5 cs6 rc0 re1 re2 re3 re5 int3 pol ad/int3 sel rc1 rc2 rc5 rc6 rc7 re1 re2 re3 re5 int3 pol ad/int3 sel fc0 fc1 wh20 wh21 wl20 wl21 ? ? 0 1 0 00 0 00 ? ? ? 00 16 dsc36 dsc34 dsc33 ? ?? ?0 0 0 00 16 0 crd31 crd32 crd33 crd34 crd35 n sfr2 area (addresses 200 16 to 21f 16 ) address register bit allocation state immediately after reset pn0 pn1 pn2 0 00 16 00 0 0 0 0 ec0 ec1 ec2 0 0 ? 00 16 ? 07 16 00 16 00 16 00 16 00 16 00 16 ? ? : fix to this bit to 0 (do not write to 1) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 cr36 cr35 cr34 cr33 cr32 cr31 cr30 0000 wh10 wh11 wl10 wl11 wh12 wh13 wl12 wl13 wh14 wl14 wh15 wl15 wh16 wl16 wh17 wl17 int2 pol int1 pol 00000 00 16
102 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. 230 16 231 16 232 16 233 16 234 16 235 16 236 16 237 16 238 16 239 16 23a 16 23b 16 23c 16 23d 16 23e 16 23f 16 220 16 221 16 222 16 223 16 224 16 225 16 226 16 227 16 228 16 229 16 22b 16 22c 16 22d 16 22e 16 22f 16 22a 16 vertical position register 1 11 (vp1 11 ) vertical position register 1 3 (vp1 3 ) vertical position register 1 7 (vp1 7 ) vertical position register 1 5 (vp1 5 ) vertical position register 1 6 (vp1 6 ) vertical position register 1 1 (vp1 1 ) vertical position register 1 2 (vp1 2 ) vertical position register 1 9 (vp1 9 ) vertical position register 1 10 (vp1 10 ) b7 b0 b7 b0 vertical position register 1 4 (vp1 4 ) vertical position register 1 12 (vp1 12 ) ? ? ? ? vp1 1 1 vertical position register 1 8 (vp1 8 ) vertical position register 2 3 (vp2 3 ) vertical position register 2 7 (vp2 7 ) vertical position register 2 5 (vp2 5 ) vertical position register 2 6 (vp2 6 ) vertical position register 2 1 (vp2 1 ) vertical position register 2 9 (vp2 9 ) vertical position register 2 10 (vp2 10 ) vertical position register 2 4 (vp2 4 ) vertical position register 2 12 (vp2 12 ) vertical position register 2 8 (vp2 8 ) vertical position register 2 2 (vp2 2 ) vertical position register 2 11 (vp2 11 ) vp1 1 2 vp1 1 3 vp1 1 4 vp1 1 5 vp1 1 6 vp1 1 7 vp1 1 8 vp1 2 1 vp1 2 2 vp1 2 3 vp1 2 4 vp1 2 5 vp1 2 6 vp1 2 7 vp1 2 8 vp1 3 1 vp1 3 2 vp1 3 3 vp1 3 4 vp1 3 5 vp1 3 6 vp1 3 7 vp1 3 8 vp1 4 1 vp1 4 2 vp1 4 3 vp1 4 4 vp1 4 5 vp1 4 6 vp1 4 7 vp1 4 8 vp1 5 1 vp1 5 2 vp1 5 3 vp1 5 4 vp1 5 5 vp1 5 6 vp1 5 7 vp1 5 8 vp1 6 1 vp1 6 2 vp1 6 3 vp1 6 4 vp1 6 5 vp1 6 6 vp1 6 7 vp1 6 8 vp1 7 1 vp1 7 2 vp1 7 3 vp1 7 4 vp1 7 5 vp1 7 6 vp1 7 7 vp1 7 8 vp1 8 1 vp1 8 2 vp1 8 3 vp1 8 4 vp1 8 5 vp1 8 6 vp1 8 7 vp1 8 8 vp1 9 1 vp1 9 2 vp1 9 3 vp1 9 4 vp1 9 5 vp1 9 6 vp1 9 7 vp1 9 8 vp1 10 1 vp1 10 2 vp1 10 3 vp1 10 4 vp1 10 5 vp1 10 6 vp1 10 7 vp1 10 8 vp1 11 1 vp1 11 2 vp1 11 3 vp1 11 4 vp1 11 5 vp1 11 6 vp1 11 7 vp1 11 8 vp1 12 1 vp1 12 2 vp1 12 3 vp1 12 4 vp1 12 5 vp1 12 6 vp1 12 7 vp1 12 8 vp2 1 1 vp2 1 2 vp2 2 1 vp2 2 2 vp2 3 1 vp2 3 2 vp2 4 1 vp2 4 2 vp2 5 1 vp2 5 2 vp2 6 1 vp2 6 2 vp2 7 1 vp2 7 2 vp2 8 1 vp2 8 2 vp2 9 1 vp2 9 2 vp2 10 1 vp2 10 2 vp2 11 1 vp2 11 2 vp2 12 1 vp2 12 2 ? ? ? ? ? ? ? ? ? ? ? ? n sfr2 area (addresses 220 16 to 248 16 ) address register bit allocation state immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : fix to this bit to 0 (do not write to 1) : < bit allocation > state immediately after reset function bit : no function bit : fix to this bit to 1 (do not write to 0) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 240 16 241 16 242 16 243 16 244 16 245 16 246 16 247 16 rom correction address 1 (high-order) rom correction enable register (rcr) rom correction address 2 (high-order) rom correction address 2 (low-order) da-h register (da-h) rom correction address 1 (low-order) da-l register (da-l) rcr0 rcr1 00 16 00 16 ? 00 16 00 16 00 16 00 16 00 16 0 0 0 0 0 00?????? 248 16 00 16 <>
103 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. internal state of processor status register and program counter at reset b7 b0 b7 b0 1 register processor status register (ps) bit allocation state immediately after reset program counter (pc h ) program counter (pc l ) contents of address ffff 16 contents of address fffe 16 i zc d b t v n? ? ? ? ? : fix to this bit to 0 (do not write to 1) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 ??
104 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: note : the following registers are the mask versions registers. values immediately after reset release bit attributes (note 1) (note 2) bits 2: bit attributes??????the attributes of control register bits are classified into 3 types : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is assigned notes 1: values immediately after reset release 0??????0 after reset release 1??????1 after reset release ???????indeterminate after reset release ??????read enabled ??????read disabled 5 r??????read ??????write enabled ??????write disabled ??????0 can be set by software, but 1 cannot be set. w??????write ] b7 b6 b5 b4 b3 b2 b1 b0 b after reset rw cpu mode register 0, 1 2 3, 4 0 1 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to 1. 0 stack page selection bit (note) (cm2) 1 b1 b0 0: 0 page 1: 1 page 10 0 5 nothing is assigned. this bit is write disable bit. when this bit is read out, the value is 0. 6, 7 0 clock switch bits (cm6, cm7) 0 0: f(x in ) = 8 mhz 0 1: f(x in ) = 12 mhz 1 0: f(x in ) = 16 mhz 1 1: do not set b7 b6 cpu mode register (cpum) (cm) [address fb 16 ] rw rw rw rw rw 5 1
105 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. port pi direction register port p3 direction register addresses 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 port p3 direction register (d3) [address 00c7 16 ] b name functions after reset rw port p3 direction register 0 0 : port p3 0 input mode 1 : port p3 0 output mode 0 1 0 : port p3 1 input mode 1 : port p3 1 output mode 0 0 port p3 direction register nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw rw r 6 refer to timer mode register 2 (address 00f5 16 ). timer 3 count source selection bit (t3sc) 0rw 2 to 5 7 refer to clock source control register (address 0216 16 ). ports p6 3 , p6 4 selection bit 0rw
106 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. port p4 direction register address 00c9 16 b7 b6 b5 b4 b3 b2 b1 b0 port p4 direction register (d4) [address 00c9 16 ] b name functions after reset rw port p4 direction register 0 1 to 4, 7 0 fix this bit to 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw r 5 0: s out pin 1: input port p4 5 port p4 5 selection bit 0 r w 6 0: s clk pin 1: input port p4 6 port p4 6 selection bit 0rw 0 osd port control register address 00cb 16 b7 b6 b5 b4 b3 b2 b1 b0 osd port control register (pf) [address 00cb 16 ] b name functions after reset r w osd port control register 0 2 3 0 : g signal output 1 : port p5 3 output 0 0 fix these bits to 0. rw rw rw rw 0, 1, 7 port p5 3 output signal selection bit (g) 4 0 : b signal output 1 : port p5 4 output 0rw port p5 4 output signal selection bit (b) 0rw 0 : r signal output 1 : port p5 2 output port p5 2 output signal selection bit (r) 5 0 : out1 signal output 1 : port p5 5 output port p5 5 output signal selection bit (out1) 6 0 : port p1 0 output 1 : out2 signal output port p1 0 output signal selection bit (out2) 000 0 0
107 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. osd control register address 00ce 16 b7 b6 b5 b4 b3 b2 b1 b0 osd control register (oc) [address 00ce 16 ] b name functions after reset r w osd control register 0 osd control bit (oc0) (see note 1) 0 : all-blocks display off 1 : all-blocks display on 0 1 scan mode selection bit (oc1) 0 : normal scnan mode 1 : bi-scan mode 0 2 0 : all bordered 1 : shadow bordered (see note 2) 0 0 4 automatic solid space control bit (oc4) 0 border type selection bit (oc2) rw rw rw rw rw 3 0 : color signal of character background part does not flash 1 : color signal of character background part flashes flash mode selection bit (oc3) 6, 7 layer mixing control bits (oc6, oc7) (see note 3) 0 0: logic sum (or) of layer 1s color and layer 2s color 0 1: layer 1s color has priority 1 0: layer 2s color has priority 1 1: do not set. b7 b6 0 : off 1 : on 0rw 5 window control bit (oc5) 0rw 0 : off 1 : on notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2 : shadow border is output at right and bottom side of the font. 3 : set 00 during displaying extra fonts. horizontal position register address 00cf 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00cf 16 ] b name functions after reset rw horizontal position register control bits of horizontal display start positions (hp0 to hp7) horizontal display start positions 4t osc 5 ( setting value of high-order 4 bits 5 16 1 + setting value of low-order 4 bits 5 16 0 ) 0rw 0 to 7 note: the setting value synchronizes with the v sync .
108 mitsubishi microcomputers single-chip 8-bit cmos micr ocomputer with closed caption decoder and on-screen displa y contr oller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. block control register i addresses 00d0 16 to 00db 16 b7 b6 b5 b4 b3 b2 b1 b0 block control register i (bci) (i=1 to 12) [addresses 00d0 16 to 00bf 16 ] (see note 1) block control register i 0, 1 display mode selection bits (bci0, bci1) (see note) indeterminate 3, 4 dot size selection bits (bci3, bci4) 5, 6 pre-divide ratio ? layer selection bit (bci5, bci6) 7 out2 output control bit (bci7) (see not 2) b1 b0 0 0: display off 0 1: osd mode 1 0: cc mode 1 1: exosd mode bc17: window top boundary bc27: window bottom boundary b name functions after reset rw rw indeterminate rw indeterminate rw indeterminate rw 2 border control bit (bci2) 0: border off 1: border on indeterminate rw notes 1: note that eprom version the block control registers at addre sses 00d0 16 to 00df 16 when programming. 2: bit 4 of the color code 1 controls out1 output when bit 7 is 0. bit 4 of the color code 1 controls out2 outp ut when bit 7 is 1. b6 b5 b4 b3 cs6 pre-divide dot size disp lay iayer 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 5 1 5 2 5 3 5 1 5 2 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 1tc 5 1/2h 1tc 5 1h 1.5tc 5 1/2h 1.5tc 5 1h 0 0 1 1 1 layer1 layer2 ? ? ? 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ratio
109 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. window register start bit position register caption position register address 00e0 16 address 00e1 16 address 00e2 16 b7 b6 b5 b4 b3 b2 b1 b0 caption position register (cps) [address 00e0 16 ] caption position register 0 to 4 0rw 0rw specification main data slice line (cp0 to cp4) 7 fix this bit to 0. 5, 6 fix these bits to 0. b after reset functions name rw 100 0r w b7 b6 b5 b4 b3 b2 b1 b0 start bit position register (sp) [address 00e1 16 ] start bit position register 0 to 6 0rw 0rw start bit generating time (sp0 to sp6) 7 dsc1 bit 7 control bit (sp7) b after reset functions name rw 0 : generation of 16 pulses 1 : generation of 16 pulses and detection of clock run-in pulse (4 to 6 pulses) time from a falling of the horizontal synchronous signal to occurrence of a start bit = 4 5 set value (00 16 to 7f 16 ) 5 reference clock period b7 b6 b5 b4 b3 b2 b1 b0 window register (wn) [address 00e2 16 ] window register 0 to 5 0rw 0rw window start time (wn0 to wn5) 6, 7 fix these bits to 0. b after reset functions name rw time from a falling of the horizontal synchronous signal to start of the window = 4 5 set value (00 16 to 3f 16 ) 5 reference clock period 00
110 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. clock run-in register 2 sync slice register address 00e7 16 address 00e3 16 clock run-in register 1 address 00e6 16 b7 b6 b5 b4 b3 b2 b1 b0 sync slice register (ssl) [address 00e3 16 ] sync slice register 7 0rw 0rw vertical synchronous signal (v sep ) generating method selection bit (ssl7) 0, 2 fix these bits to 1. b after reset functions name rw 0: method 1 1: method 2 000101 0rw 1, 3 to 6 fix these bits to 0. 0 b7 b6 b5 b4 b3 b2 b1 b0 clock run-in register 1 (cr1) [address 00e6 16 ] clock run-in register 1 0 to 3 0r w clock run-in count value of main-data slice line (cr10 to cr13) 0rw 4, 6 fix these bits to 1. b after reset functions name rw 101 0rw 5, 7 fix these bits to 0. 0 b7 b6 b5 b4 b3 b2 b1 b0 clock run-in register 2 (cr2) [address 00e7 16 ] clock run-in register 2 0rw 0, 2 to 4, 7 fix these bits to 1. b after reset functions name rw 001 0rw 5, 6 fix these bits to 0. 1111 1 start bit detecting method selection bit (cr21) 0: method 1 1: method 2 0rw
111 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. clock run-in detect register 2 clock run-in detect register i addresses 00e8 16 , 0208 16 address 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register i (crdi) (i=1, 3) [addresses 00e8 16 , 0208 16 ] clock run-in detect register i 0 to 2 0r w test bits 0r 3 to 7 clock run-in detection bits (crdi3 to crdi7) b after reset functions name rw read-only number of reference clock s to be counted one clock run- in pulse period b7 b6 b5 b4 b3 b2 b1 b0 clock run-in detect register 2 (crd2) [address 00e9 16 ] clock run-in detect register 2 b after reset functions name rw 0rw 0 to 2 0r w clock run-in pulses for sampling (crd20 to crd22) 3 to 7 data clock generating time (crd23 to crd27) b2 b1 b0 0 0 0 : not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse time from detection of a start bit to occurrence of a data clock = (13 + set value) 5 reference clock period
112 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. data slicer control register 1 address 00ea 16 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 1(dsc1) [address 00ea 16 ] b bit functions after reset r w data slicer control register 1 0 0 rw 0 rw 0 rw indeterminate r 0 0: data slicer stopped 1: data slicer operating data slicer control bit (dsc10) fix these bits to 0. 3, 4, 6 00 1, 2 field to be sliced data selection bit (dsc11, dsc12) 5 field determination flag (dsc15) hsep vsep hsep vsep 0 : 1 : definition of fields 1 (f1) and 2 (f2) hsep v sync vsep f1 : hsep v sync vsep f2 : field of main data slice line b2 b1 0 0 f2 0 1 f1 1 0 f1 and f2 1 1 f1 and f2 f2 f1 f2 f1 field for setting refernce voltage 7 0: data is not yet latched 1: data is latched data latch completion flag for caption data in main data slice line (dsc17) indeterminate r w
113 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. a-d control register data slicer control register 2 address 00eb 16 address 00ef 16 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 2 (dsc2) [address 00eb 16 ] b name functions after reset r w data slicer control register 2 0 1 0r w indeterminate r 0r w 0 0: stopped 1: operating timing signal generating circuit control bit (dsc20) 2, 7 read-only test bit 3, 4, 6 fix these bits to 0. 5 0: match 1: mis match v-pulse shape determination flag (dsc25) indeterminate r 00 0: video signal 1: h sync signal reference clock source selection bit (dsc21) b7 b6 b5 b4 b3 b2 b1 b0 a-d control register (adcon) [address 00ef 16 ] b after reset rw a-d control register 0 to 2 analog input pin selection bits (adin0 to adin2) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 1 1 0 : 1 1 1 : 4 v cc connection selection bit (advref) 0: off 1: on 0 indeterminate do not set. 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. rw rw r 3 a-d conversion completion bit (adstr) 0: conversion in progress 1: convertion completed indeterminate rw 0 5, 7 fix these bits to 0. r 00 indeterminate 0r w
114 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. timer mode register 1 address 00f4 16 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w timer mode register 1 0 1 2 3 4 name functions timer 1 count source selection bit 1 (tm10) 0: f(x in )/16 or f(x cin )/16 (note) 1: count source selected by bit 5 of tm1 timer 2 count source selection bit 1 (tm11) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin timer 1 count stop bit (tm12) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop timer 2 count source selection bit 2 (tm14) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 timer 5 count source selection bit 2 (tm16) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 timer 6 internal count source selection bit (tm17) 0w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow
115 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. i 2 c data shift register timer mode register 2 address 00f5 16 address 00f6 16 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset rw timer mode register 2 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0rw 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw rw 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 0 0 : f(x in )/16 or f(x cin )/16 (see note) 0 1 : f(x cin ) 1 0 : 1 1 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 0 0 : timer 3 overflow signal 0 1 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x in )/2 or f(x cin )/2 (see note) 1 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. b7 b6 b5 b4 b3 b2 b1 b0 i c data shift register1(s0) [address 00f6 16 ] b functions after reset rw i c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate 2 2 note: 2 to write data into the i c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw
116 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. i 2 c status register i 2 c address register address 00f7 16 address 00f8 16 b7 b6 b5 b4 b3 b2 b1 b0 0 read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) 0: read 1: write 0 0 the address data transmitted from the master is compared with the contents of these bits. i 2 c address register i 2 c address register (s0d) [address 00f7 16 ] b name functions after reset rw r rw b7 b6 b5 b4 b3 b2 b1 b0 i 2 c status register (s1) [address 00f8 16 ] i 2 c status register 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 0 0 b name functions after reset rw communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = 0 1 : last bit = 1 last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate r r r r r rw 0 rw
117 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. i 2 c clock control register i 2 c control register address 00f9 16 address 00fa 16 b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bus interface use enable bit (eso) 0 : disabled 1 : enabled 4 data format selection bit (als) 0 : addressing mode 1 : free data format 5 addressing format selection bit (10bit sad) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 connection control bits between i c-bus interface and ports b7 b6 connection port (see note) 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1 scl2, sda2 0 0 0 0 0 i 2 c control register (s1d : address 00f9 16 ) i 2 c control register b name functions after reset rw note: when using ports p1 1 -p1 4 as i c-bus interface, the output structure changes automaticall y from cmos output to n-channel open-drain out p ut. 2 2 rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00fa 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0 : standard clock mode 1 : high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0 : ack is returned. 1 : ack is not returned. 0 : no ack clock 1 : ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 333 03 setup disabled 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 4000khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 setup value of ccr4Cccr0 rw rw rw rw
118 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. interrupt request register 1 cpu mode register address 00fb 16 address 00fc 16 b7 b6 b5 b4 b3 b2 b1 b0 b after reset rw cpu mode register 0, 1 2 3, 4 0 1 name functions processor mode bits (cm0, cm1) 0 0: single-chip mode 0 1: 1 0: not available 1 1: fix these bits to 1. 1 stack page selection bit (cm2) (see note) 1 b1 b0 0: 0 page 1: 1 page 10 0 5 6 main clock (x in Cx out ) stop bit (cm6) cpu mode register (cpum) (cm) [address fb 16 ] rw rw rw rw rw x cout drivability selection bit (cm5) 0: low drive 1: high drive 0: oscillating 1: stopped 7 internal system clock selection bit (cm7) rw 0: x in Cx out selected (high-speed mode) 1: x cin Cx cout selected (high-speed mode) note: this bit is set to 1 after the reset release. b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 osd interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 a-d conversion ? int3 interrupt request bit (adr) 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 can be set by software, but 1 cannot be set. 16 ] r r r r r r r r nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 1 0 0
119 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. interrupt control register 1 interrupt request register 2 address 00fd 16 address 00fe 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name functions after reset rw interrupt request register 2 0 int1 interrupt request bit (int1r) 0 : no interrupt request issued 1 : interrupt request issued 1 data slicer interrupt request bit (dsr) 2 serial i/o interrupt request bit (sior) 3 4 int2 interrupt request bit (int2r) 5 7 fix this bit to 0. 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] : 0 can be set by software, but 1 cannot be set. 0 0 ] 0 0 ] 0 ] 0 ] 0 : no interrupt request issued 1 : interrupt request issued 16 ] r r r r ] r r ] rw f(x in )/4096 interrupt request bit (1msr) 0 : no interrupt request issued 1 : interrupt request issued multi-master i 2 c-bus interrupt request bit (iicr) 0 : no interrupt request issued 1 : interrupt request issued 6 timer 5 ? 6 interrupt request bit (t56r) 0 : no interrupt request issued 1 : interrupt request issued 0 ] r b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 osd interrupt enable bit (crte) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw rw r 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vscr) 0 : interrupt disabled 1 : interrupt enabled 0rw 6 a-d conversion ? int3 interrupt enable bit (ade) 0 : interrupt disabled 1 : interrupt enabled 0rw
120 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. clock run-in register 3 interrupt control register 2 address 00ff 16 address 0209 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset rw interrupt control register 2 0 int1 interrupt enable bit (int1e) 0 : interrupt disabled 1 : interrupt enabled 1 data slicer interrupt enable bit (dsr) 2 serial i/o interrupt enable bit (sioe) 3 4 int2 interrupt enable bit (int2e) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 rw rw rw rw rw f(x in )/4096 interrupt enable bit (1mse) 0 : interrupt disabled 1 : interrupt enabled 5 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled 0rw 6 timer 5 ? 6 interrupt enable bit (t56e) 0 : interrupt disabled 1 : interrupt enabled 0rw 7 timer 5 ? 6 interrupt switch bit (tm56s) 0 : timer 5 1 : timer 6 0rw b7 b6 b5 b4 b3 b2 b1 b0 clock run-in register 3 (cr3) [address 0209 16 ] b name functions after reset r w clock run-in register 3 0 to 3 0rw 4 r w indeterminate r w clock run-in count value of sub-data slice line (cr30 to cr33) 5 6 interrupt mode selection bit (cr36) indeterminate rw 0: data is not latched yet 1: data is latched data latch completion flag for caption data in sub- data slice line (cr34) data slice line selection bit for interrupt request (cr35) 0: main data slice line 1: sub- data slice line 0: interrupt occurs at end of data slice line 1: interrupt occurs at completion of caption data latch nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 7 indeterminate indeterminate r
121 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. pwm mode register 2 pwm mode register 1 address 020a 16 address 020b 16 b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pw) [address 020b 16 ] b after reset rw pwm mode register 2 0 1 2 3 4 0 name functions p0 4 /pwm0 output selection bit (pw0) 0 : p0 4 output 1 : pwm0 output p0 6 /pwm2 output selection bit (pw2) 0 : p0 6 output 1 : pwm2 output p0 7 /pwm3 output selection bit (pw3) 0 : p0 7 output 1 : pwm3 output p0 0 /pwm4 output selection bit (pw4) 0 : p0 0 output 1 : pwm4 output 5 p0 1 /pwm5 output selection bit (pw5) 0: p0 1 output 1: pwm5 output 7 fix this bit to 0. p0 5 /pwm1 output selection bit (pw1) 0 : p0 5 output 1 : pwm1 output 0 0 0 0 0 0 rw rw rw rw rw rw rw 0 6 p0 2 /pwm6 output selection bit (pw6) 0: p0 2 output 1: pwm6 output 0rw b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 1 (pn) [address 020a 16 ] b after reset rw pwm mode register 1 0 4 to 7 1 0 name functions da/p0 3 output selection bit (pn1) indeterminate 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : p0 3 output 1 : da output rw r rw pwm counts source selection bit (pn0) 0 : count source supply 1 : count source stop 2 da output polarity selection bit (pn2) 0 0 : positive polarity 1 : negative polarity rw 3 pwm output polarity selection bit (pn3) 0 0 : positive polarity 1 : negative polarity rw
122 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. data slicer control register 3 sync pulse counter register address 020f 16 address 0210 16 b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (syc) [address 020f 16 ] r w sync pulse counter register 0 to 4 0r 6, 7 0 r count value (syc0 to syc4) 5 0rw count source (syc5) 0: h sync signal 1: composite sync signal b after reset functions name nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 3 (dsc3) [address 0210 16 ] b bit functions after reset r w data slicer control register 3 0 0rw 0rw 0: main data slice line 1: sub-data slice line line selection bit for slice voltage (dsc30) 3 to 7 1, 2 field to be sliced data selection bit (dsc31, dsc32) definition of fields 1 (f1) and 2 (f2) hsep v sync vsep f1 : hsep v sync vsep f2 : field of sub- data slice line b2 b1 0 0 f2 0 1 f1 1 0 f1 and f2 1 1 f1 and f2 f2 f1 f2 f1 field for setting refernce voltage setting bit of sub-data slice line (dsc33 to dsc37) 0rw
123 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. serial i/o mode register interrupt input polarity register address 0212 16 address 0213 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register (ip) [address 0212 16 ] b name functions after reset r w interrupt input polarity register 0 0 to 2, 5 fix these bits to 0. rw int1 polarity switch bit (int1pol) 0 0 3 0 : positive polarity 1 : negative polarity 4 0 : positive polarity 1 : negative polarity 6 int2 polarity switch bit ( int2pol ) int3 polarity switch bit ( int3pol ) 0rw rw rw 0 : positive polarity 1 : negative polarity 0000 0 0 : positive polarity 1 : negative polarity 7 a-d conversion ? int3 interrupt source selection bit (re7) rw b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 0213 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) b1 b0 0 0: f(x in )/4 or f(x cin )/4 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 synchronous clock selection bit (sm2) 3 port function selection bit (sm3) 6, 7 5 transfer direction selection bit (sm5) 0 0: p1 1 , p1 3 1: scl1, sda1 0: external clock 1: internal clock 0: lsb first 1: msb first fix these bits to 0. 0 0 0 0 0 0 rw rw rw rw rw rw 0 4 port function selection bit (sm4) 0: p1 2 , p1 4 1: scl2, sda2
124 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. clock source control register address 0216 16 b7 b6 b5 b4 b3 b2 b1 b0 clock source control register (cs) [address 0216 16 ] b name functions after reset rw clock source control register 0 cc mode clock selection bit (cs0) 0rw 1, 2 osd mode clock selection bits (cs1, cs2) 0: data slicer clock 1: osc1 clock 0rw 3 exosd mode clock selection bit (cs3) 0: data slicer clock 1: osc1 clock 0rw 4, 5 0 w 6 pre-divide ratio of layer 2 selection bit (cs6) 0: 5 1 1: 5 2 0 rw 7 0 0: data slicer clock 0 1: osc1 clock 1 0: main clock (see note 1) 1 1: do not set b2 b1 test bit (see note 3) r osd oscillating mode selection bits (cs4, cs5) 0 0: 32 khz oscillating mode 0 1: input ports p6 3 , p6 4 (see note 2) 1 0: lc oscillating mode 1 1: ceramic ? quartz-crystal oscillating mode b5 b4 notes 1: when setting 10 2 , main clock is set as a clock in the cc mode and exosd mode regardless of bits 0, 3. 2: when selecting input ports p6 3 and p6 4 , set bit 7 at address 00c7 16 to 1. 3: be sure to set bit 7 to 0 for program of the mask and the eprom versions. for the emulator mcu version (m37274erss), be sure to set bit 7 to 1 when using the data slicer clock for software debugging. rw 0
125 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. raster color register i/o polarity control register address 0217 16 address 0218 16 b7 b6 b5 b4 b3 b2 b1 b0 i/o polarity control register (pc) [address 0217 16 ] b name functions after reset r w i/o polarity control register 0h sync input polarity switch bit (pc0) 0 : positive polarity input 1 : negative polarity input 0 1 0 : positive polarity input 1 : negative polarity input 0 2 r, g, b output polarity switch bit (pc2) 0 : positive polarity output 1 : negative polarity output 0 3 0 v sync input polarity switch bit (pc1) rw rw rw r note: refer to the corresponding figure (p62). 0 : at even field at odd field 1 : at even field at odd field 4 out1 output polarity switch bit (pc4) 0 : positive polarity output 1 : negative polarity output 0 5 out2 output polarity switch bit (pc5) 0 : positive polarity output 1 : negative polarity output 0 6 display dot line selection bit (pc6) (see note) 0 7 field determination flag (pc7) 0 : even field 1 : odd field 1 rw rw rw r nothing is assigned. ths bit is a write disable bit. when this bit is read out, the value is 0. b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 0218 16 ] b name functions after reset r w raster color register 0 raster color r control bit (rc0) 0 : no output 1 : output 0 1 raster color g control bit (rc1) 0 : no output 1 : output 0 2 0 : no output 1 : output 0 raster color b control bit (rc2) rw rw rw 3, 4 0 6 raster color out2 control bit (rc6) 0 rw rw 5 0 : no output 1 : output raster color out1 control bit (rc5) 0 : no output 1 : output 7 0r 0rw 00 osd interrupt source selection bit (rc7) 0 : interrupt occurs at end of osd or exosd block display 1 : interrupt occurs at end of cc mode block display nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0.
126 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. border color register extra font color register address 0219 16 address 021b 16 b7 b6 b5 b4 b3 b2 b1 b0 extra font color register (ec) [address 0219 16 ] b after reset rw extra font color register 0 3, 4 1 0 name functions extra font color g control bit (ec1) 0 fix these bits to 0. 0 : no output 1 : output rw r rw extra font color r control bit (ec0) 0 : no output 1 : output 2 extra font color b control bit (ec2) 0 0 : no output 1 : output rw 0rw 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 5 to 7 0 b7 b6 b5 b4 b3 b2 b1 b0 border color register (fc) [address 021b 16 ] b after reset rw border color register 0 3, 4 1 0 name functions border color g control bit (fc1) 0 fix these bits to 0. 0 : no output 1 : output rw r rw border color r control bit (fc0) 0 : no output 1 : output 2 border color b control bit (fc2) 0 0 : no output 1 : output rw 0rw 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 5 to 7 0
127 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. window h register 2 window h register 1 address 021c 16 address 021e 16 window l register 1 address 021d 16 b7 b6 b5 b4 b3 b2 b1 b0 window h register 1 (wh1) [address 021c 16 ] b name functions after reset r w window h register 1 0 to 7 control bits of window top boundary (wn10 to wn17) (see note 1) top boundary position (low-order 8 bits) t h 5 (setting value of low-order 2 bits of wh2 5 16 2 + setting value of high-order 4 bits of wh1 5 16 1 + setting value of low-order 4 bits of wh1 5 16 0 ) indeterminate rw notes 1: set values except 00 16 to the wh1 when wh2 is 00 16 . 2: t h is cycle of h sync . b7 b6 b5 b4 b3 b2 b1 b0 window l register 1 (wl1) [address 021d 16 ] b name functions after reset r w window l register 1 0 to 7 control bits of window top boundary (wl10 to wl17) (see note 1) top boundary position (low-order 8 bits) t h 5 (setting value of low-order 2 bits of wl2 5 16 2 + setting value of high-order 4 bits of wl1 5 16 1 + setting value of low-order 4 bits of wl1 5 16 0 ) indeterminate rw notes 1: set values fit for the following condition: (wh1+wh2)<(wl1+wl2) 2: t h is cycle of h sync . b7 b6 b5 b4 b3 b2 b1 b0 window h register 2 (wh2) [address 021e 16 ] b name functions after reset r w window h register 2 0, 1 control bits of window top boundary (wn20 to wn27) (see note 1) top boundary position (high-order 2 bits) t h 5 (setting value of low-order 2 bits of wh2 5 16 2 + setting value of high-order 4 bits of wh1 5 16 1 + setting value of low-order 4 bits of wh1 5 16 0 ) indeterminate rw notes 1: set values except 00 16 to the wh1 when wh2 is 00 16 . 2: t h is cycle of h sync . nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 indeterminate r
128 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. vertical position register 2i window l register 2 address 021f 16 addresses 0230 16 to 023b 16 vertical position register 1i addresses 0220 16 to 022b 16 b7 b6 b5 b4 b3 b2 b1 b0 window l register 2 (wl2) [address 021f 16 ] b name functions after reset r w window l register 2 0, 1 control bits of window top boundary (wl20 to wl27) (see note 1) top boundary position (high-order 2 bits) t h 5 (setting value of low-order 2 bits of wl2 5 16 2 + setting value of high-order 4 bits of wl1 5 16 1 + setting value of low-order 4 bits of wl1 5 16 0 ) indeterminate rw notes 1: set values fit for the following condition: (wh1+wh2)<(wl1+wl2) 2: t h is cycle of h sync . nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 indeterminate r b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 1i (vp1i) (i = 1 to 12) [addresses 0220 16 to 022b 16 ] b name functions after reset r w vertical position register 1i 0 to 7 control bits of vertical display start positions (vp1i0 to vp1i7) (see note 1) vertical display start positions (low-order 8 bits) t h 5 (setting value of low-order 2 bits of vp2i 5 16 2 + setting value of low-order 4 bits of vp1i 5 16 1 + setting value of low-order 4 bits of vp1i 5 16 0 ) indeterminate rw notes 1: set values except 00 16 01 16 to vp1i when vp2i is 00 16 . 2: t h is cycle of h sync . b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 2i (vp2i) (i = 1 to 12) [addresses 0230 16 to 023b 16 ] b name functions after reset r w vertical position register 2i 0, 1 control bits of vertical display start positions (vp1i0 to vp1i7) (see note 1) vertical display start positions (high-order 2 bits) t h 5 (setting value of low-order 2 bits of vp2i 5 16 2 + setting value of low-order 4 bits of vp1i 5 16 1 + setting value of low-order 4 bits of vp1i 5 16 0 ) indeterminate rw nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 indeterminate r notes 1: set values except 00 16 01 16 to vp1i when vp2i is 00 16 . 2: t h is cycle of h sync .
129 mitsubishi microcomputers single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37274ma-xxxsp preliminary notice: this is not a final specification. some paramentic limits are subject to change. rom correction enable register address 0246 16 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 0246 16 ] b after reset rw rom correction enable register 0 block 1 enable bit (rc0) name functions 0: disabled 1: enabled 1 block 2 enable bit (rc1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 rw rw r 0 0 2, 3 fix these bits to 0. 0 rw
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rev. rev. no. date 1.0 first edition 2.0 information about copywright note, revision number, release date added (last page). revision description list (1/1) revision description 971130 m37274ma-xxxsp data sheet 9706
